Lines Matching +full:0 +full:x02011000
23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
114 polling-delay-passive = <0>;
115 polling-delay = <0>;
134 polling-delay-passive = <0>;
135 polling-delay = <0>;
154 polling-delay-passive = <0>;
155 polling-delay = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
194 polling-delay-passive = <0>;
195 polling-delay = <0>;
214 polling-delay-passive = <0>;
215 polling-delay = <0>;
234 polling-delay-passive = <0>;
235 polling-delay = <0>;
254 polling-delay-passive = <0>;
255 polling-delay = <0>;
276 reg = <0x0 0x0>;
291 reg = <0x40000000 0x1000000>;
297 reg = <0x41000000 0x200000>;
307 #clock-cells = <0>;
313 #clock-cells = <0>;
320 #clock-cells = <0>;
333 snps,blen = <16 0 0 0 0 0 0>;
352 reg = <0x00108000 0x1000>;
353 qcom,ipc = <&l2cc 0x8 2>;
371 reg = <0x00500000 0x1000>;
377 reg = <0x00700000 0x1000>;
381 reg = <0xc0 0x4>;
384 reg = <0x400 0xb>;
387 reg = <0x410 0xb>;
393 reg = <0x00800000 0x4000>;
396 gpio-ranges = <&qcom_pinmux 0 0 69>;
519 reg = <0x00900000 0x4000>;
539 reg = <0x01200600 0x100>;
548 reg = <0x02000000 0x1000>,
549 <0x02002000 0x1000>;
565 reg = <0x0200a000 0x100>;
569 cpu-offset = <0x80000>;
574 reg = <0x02011000 0x1000>;
577 #clock-cells = <0>;
582 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
586 #clock-cells = <0>;
591 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
597 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
601 #clock-cells = <0>;
606 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
612 reg = <0x03000000 0x0000FFFF>;
619 reg = <0x100f8800 0x8000>;
632 reg = <0x10000000 0xcd00>;
643 reg = <0x100f8800 0x30>;
646 #phy-cells = <0>;
653 reg = <0x100f8830 0x30>;
656 #phy-cells = <0>;
665 reg = <0x110f8800 0x8000>;
678 reg = <0x11000000 0xcd00>;
689 reg = <0x110f8800 0x30>;
692 #phy-cells = <0>;
699 reg = <0x110f8830 0x30>;
702 #phy-cells = <0>;
709 reg = <0x12182000 0x8000>;
714 qcom,ee = <0>;
719 reg = <0x12402000 0x8000>;
724 qcom,ee = <0>;
735 arm,primecell-periphid = <0x00051180>;
737 reg = <0x12180000 0x2000>;
755 arm,primecell-periphid = <0x00051180>;
756 reg = <0x12400000 0x2000>;
773 reg = <0x12440000 0x100>;
787 reg = <0x12450000 0x100>,
788 <0x12400000 0x03>;
798 reg = <0x12460000 0x1000>;
803 #size-cells = <0>;
812 reg = <0x12480000 0x100>;
824 reg = <0x12490000 0x1000>,
825 <0x12480000 0x1000>;
834 reg = <0x124a0000 0x1000>;
842 #size-cells = <0>;
849 reg = <0x16300000 0x100>;
861 reg = <0x16340000 0x1000>,
862 <0x16300000 0x1000>;
871 reg = <0x16380000 0x1000>;
879 #size-cells = <0>;
885 reg = <0x16500000 0x100>;
899 reg = <0x16580000 0x1000>;
906 #size-cells = <0>;
913 reg = <0x16580000 0x1000>;
920 #size-cells = <0>;
930 reg = <0x16600000 0x100>;
940 reg = <0x16640000 0x1000>,
941 <0x16600000 0x1000>;
950 reg = <0x16680000 0x1000>;
957 #size-cells = <0>;
965 reg = <0x18300000 0x100000>;
978 qcom,ee = <0>;
986 reg = <0x1a200000 0x100>;
999 reg = <0x1a240000 0x1000>,
1000 <0x1a200000 0x1000>;
1009 reg = <0x1a280000 0x1000>;
1017 #size-cells = <0>;
1022 reg = <0x1a280000 0x1000>;
1030 #size-cells = <0>;
1036 reg = <0x1a400000 0x100>;
1041 reg = <0x1a500000 0x200>;
1048 reg = <0x1ac00000 0x800>;
1050 pinctrl-0 = <&nand_pins>;
1063 #size-cells = <0>;
1070 reg = <0x1b400000 0x200>;
1075 #phy-cells = <0>;
1081 reg = <0x1b500000 0x1000
1082 0x1b502000 0x80
1083 0x1b600000 0x100
1084 0x0ff00000 0x100000>;
1087 linux,pci-domain = <0>;
1088 bus-range = <0x00 0xff>;
1093 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
1094 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
1099 interrupt-map-mask = <0 0 0 0x7>;
1100 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1101 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1102 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1103 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1123 pinctrl-0 = <&pcie0_pins>;
1132 reg = <0x1b700000 0x1000
1133 0x1b702000 0x80
1134 0x1b800000 0x100
1135 0x31f00000 0x100000>;
1139 bus-range = <0x00 0xff>;
1144 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
1145 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
1150 interrupt-map-mask = <0 0 0 0x7>;
1151 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1152 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1153 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1154 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1174 pinctrl-0 = <&pcie1_pins>;
1183 reg = <0x1b900000 0x1000
1184 0x1b902000 0x80
1185 0x1ba00000 0x100
1186 0x35f00000 0x100000>;
1190 bus-range = <0x00 0xff>;
1195 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
1196 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
1201 interrupt-map-mask = <0 0 0 0x7>;
1202 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1203 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1204 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1205 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1225 pinctrl-0 = <&pcie2_pins>;
1234 reg = <0x1bb00000 0x000001FF>;
1239 reg = <0x28000000 0x1000>;
1255 reg = <0x28100000 0x10000>;
1261 reg = <0x29000000 0x180>;
1284 reg = <0x37000000 0x200000>;
1308 reg = <0x37200000 0x200000>;
1332 reg = <0x37400000 0x200000>;
1356 reg = <0x37600000 0x200000>;