Lines Matching +full:gcc +full:- +full:apq8084
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
12 compatible = "qcom,apq8084";
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
22 no-map;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 enable-method = "qcom,kpss-acc-v2";
35 next-level-cache = <&L2>;
38 cpu-idle-states = <&CPU_SPC>;
45 enable-method = "qcom,kpss-acc-v2";
46 next-level-cache = <&L2>;
49 cpu-idle-states = <&CPU_SPC>;
56 enable-method = "qcom,kpss-acc-v2";
57 next-level-cache = <&L2>;
60 cpu-idle-states = <&CPU_SPC>;
67 enable-method = "qcom,kpss-acc-v2";
68 next-level-cache = <&L2>;
71 cpu-idle-states = <&CPU_SPC>;
74 L2: l2-cache {
76 cache-level = <2>;
77 cache-unified;
81 idle-states {
83 compatible = "qcom,idle-state-spc",
84 "arm,idle-state";
85 entry-latency-us = <150>;
86 exit-latency-us = <200>;
87 min-residency-us = <2000>;
99 compatible = "qcom,scm-apq8084", "qcom,scm";
100 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
101 clock-names = "core", "bus", "iface";
105 thermal-zones {
106 cpu0-thermal {
107 polling-delay-passive = <250>;
108 polling-delay = <1000>;
110 thermal-sensors = <&tsens 5>;
126 cpu1-thermal {
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
130 thermal-sensors = <&tsens 6>;
146 cpu2-thermal {
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
150 thermal-sensors = <&tsens 7>;
166 cpu3-thermal {
167 polling-delay-passive = <250>;
168 polling-delay = <1000>;
170 thermal-sensors = <&tsens 8>;
187 cpu-pmu {
188 compatible = "qcom,krait-pmu";
194 compatible = "fixed-clock";
195 #clock-cells = <0>;
196 clock-frequency = <19200000>;
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <32768>;
207 compatible = "arm,armv7-timer";
212 clock-frequency = <19200000>;
218 qcom,rpm-msg-ram = <&rpm_msg_ram>;
219 memory-region = <&smem_mem>;
225 #address-cells = <1>;
226 #size-cells = <1>;
228 compatible = "simple-bus";
230 intc: interrupt-controller@f9000000 {
231 compatible = "qcom,msm-qgic2";
232 interrupt-controller;
233 #interrupt-cells = <3>;
244 compatible = "qcom,apq8084-rpm-stats";
249 compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
251 #address-cells = <1>;
252 #size-cells = <1>;
259 tsens_s0_p1: s0-p1@d1 {
264 tsens_s1_p1: s1-p1@d2 {
269 tsens_s2_p1: s2-p1@d2 {
274 tsens_s3_p1: s3-p1@d3 {
279 tsens_s4_p1: s4-p1@d4 {
284 tsens_s5_p1: s5-p1@d4 {
289 tsens_s6_p1: s6-p1@d5 {
294 tsens_s7_p1: s7-p1@d6 {
299 tsens_s8_p1: s8-p1@d7 {
309 tsens_s9_p1: s9-p1@d8 {
324 tsens_s0_p2: s0-p2@da {
329 tsens_s1_p2: s1-p2@db {
334 tsens_s2_p2: s2-p2@dc {
339 tsens_s3_p2: s3-p2@dc {
344 tsens_s4_p2: s4-p2@dd {
349 tsens_s5_p2: s5-p2@de {
354 tsens_s6_p2: s6-p2@df {
359 tsens_s7_p2: s7-p2@e0 {
364 tsens_s8_p2: s8-p2@e0 {
369 tsens_s9_p2: s9-p2@e1 {
379 tsens_s5_p2_backup: s5-p2_backup@e3 {
389 tsens_s6_p2_backup: s6-p2_backup@e4 {
394 tsens_s7_p2_backup: s7-p2_backup@e4 {
399 tsens_s8_p2_backup: s8-p2_backup@e5 {
404 tsens_s9_p2_backup: s9-p2_backup@e6 {
419 tsens_s0_p1_backup: s0-p1_backup@441 {
424 tsens_s1_p1_backup: s1-p1_backup@442 {
429 tsens_s2_p1_backup: s2-p1_backup@442 {
434 tsens_s3_p1_backup: s3-p1_backup@443 {
439 tsens_s4_p1_backup: s4-p1_backup@444 {
444 tsens_s5_p1_backup: s5-p1_backup@444 {
449 tsens_s6_p1_backup: s6-p1_backup@445 {
454 tsens_s7_p1_backup: s7-p1_backup@446 {
464 tsens_s8_p1_backup: s8-p1_backup@448 {
469 tsens_s9_p1_backup: s9-p1_backup@448 {
484 tsens_s0_p2_backup: s0-p2_backup@44b {
489 tsens_s1_p2_backup: s1-p2_backup@44c {
494 tsens_s2_p2_backup: s2-p2_backup@44c {
499 tsens_s3_p2_backup: s3-p2_backup@44d {
504 tsens_s4_p2_backup: s4-p2_backup@44e {
510 tsens: thermal-sensor@fc4a9000 {
511 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
514 nvmem-cells = <&tsens_mode>,
541 nvmem-cell-names = "mode",
570 interrupt-names = "uplow";
571 #thermal-sensor-cells = <1>;
574 #address-cells = <1>;
575 #size-cells = <1>;
577 compatible = "arm,armv7-timer-mem";
579 clock-frequency = <19200000>;
582 frame-number = <0>;
590 frame-number = <1>;
597 frame-number = <2>;
604 frame-number = <3>;
611 frame-number = <4>;
618 frame-number = <5>;
625 frame-number = <6>;
632 saw0: power-controller@f9089000 {
633 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
637 saw1: power-controller@f9099000 {
638 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
642 saw2: power-controller@f90a9000 {
643 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
647 saw3: power-controller@f90b9000 {
648 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
652 saw_l2: power-controller@f9012000 {
658 acc0: power-manager@f9088000 {
659 compatible = "qcom,kpss-acc-v2";
664 acc1: power-manager@f9098000 {
665 compatible = "qcom,kpss-acc-v2";
670 acc2: power-manager@f90a8000 {
671 compatible = "qcom,kpss-acc-v2";
676 acc3: power-manager@f90b8000 {
677 compatible = "qcom,kpss-acc-v2";
687 gcc: clock-controller@fc400000 {
688 compatible = "qcom,gcc-apq8084";
689 #clock-cells = <1>;
690 #reset-cells = <1>;
691 #power-domain-cells = <1>;
702 clock-names = "xo",
714 compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
716 #hwlock-cells = <1>;
720 compatible = "qcom,rpm-msg-ram";
725 compatible = "qcom,apq8084-pinctrl";
727 gpio-controller;
728 gpio-ranges = <&tlmm 0 0 147>;
729 #gpio-cells = <2>;
730 interrupt-controller;
731 #interrupt-cells = <2>;
736 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
739 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
740 clock-names = "core", "iface";
745 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
747 reg-names = "hc", "core";
749 interrupt-names = "hc_irq", "pwr_irq";
750 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
751 <&gcc GCC_SDCC1_APPS_CLK>,
753 clock-names = "iface", "core", "xo";
758 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
760 reg-names = "hc", "core";
762 interrupt-names = "hc_irq", "pwr_irq";
763 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
764 <&gcc GCC_SDCC2_APPS_CLK>,
766 clock-names = "iface", "core", "xo";
771 compatible = "qcom,spmi-pmic-arb";
772 reg-names = "core", "intr", "cnfg";
776 interrupt-names = "periph_irq";
780 #address-cells = <2>;
781 #size-cells = <0>;
782 interrupt-controller;
783 #interrupt-cells = <4>;
788 compatible = "qcom,apq8084-rpm-proc", "qcom,rpm-proc";
790 smd-edge {
793 qcom,smd-edge = <15>;
795 rpm-requests {
796 compatible = "qcom,rpm-apq8084";
797 qcom,smd-channels = "rpm_requests";
799 regulators-0 {
800 compatible = "qcom,rpm-pma8084-regulators";