Lines Matching +full:qcom +full:- +full:tsens
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "qcom,apq8064";
17 interrupt-parent = <&intc>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
26 no-map;
31 no-map;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "qcom,krait";
41 enable-method = "qcom,kpss-acc-v1";
44 next-level-cache = <&L2>;
45 qcom,acc = <&acc0>;
46 qcom,saw = <&saw0>;
47 cpu-idle-states = <&CPU_SPC>;
51 compatible = "qcom,krait";
52 enable-method = "qcom,kpss-acc-v1";
55 next-level-cache = <&L2>;
56 qcom,acc = <&acc1>;
57 qcom,saw = <&saw1>;
58 cpu-idle-states = <&CPU_SPC>;
62 compatible = "qcom,krait";
63 enable-method = "qcom,kpss-acc-v1";
66 next-level-cache = <&L2>;
67 qcom,acc = <&acc2>;
68 qcom,saw = <&saw2>;
69 cpu-idle-states = <&CPU_SPC>;
73 compatible = "qcom,krait";
74 enable-method = "qcom,kpss-acc-v1";
77 next-level-cache = <&L2>;
78 qcom,acc = <&acc3>;
79 qcom,saw = <&saw3>;
80 cpu-idle-states = <&CPU_SPC>;
83 L2: l2-cache {
85 cache-level = <2>;
86 cache-unified;
89 idle-states {
91 compatible = "qcom,idle-state-spc",
92 "arm,idle-state";
93 entry-latency-us = <400>;
94 exit-latency-us = <900>;
95 min-residency-us = <3000>;
105 thermal-zones {
106 cpu0-thermal {
107 polling-delay-passive = <250>;
108 polling-delay = <1000>;
110 thermal-sensors = <&tsens 7>;
127 cpu1-thermal {
128 polling-delay-passive = <250>;
129 polling-delay = <1000>;
131 thermal-sensors = <&tsens 8>;
148 cpu2-thermal {
149 polling-delay-passive = <250>;
150 polling-delay = <1000>;
152 thermal-sensors = <&tsens 9>;
169 cpu3-thermal {
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
173 thermal-sensors = <&tsens 10>;
191 cpu-pmu {
192 compatible = "qcom,krait-pmu";
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <19200000>;
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <27000000>;
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <32768>;
217 compatible = "qcom,sfpb-mutex";
219 #hwlock-cells = <1>;
223 compatible = "qcom,smem";
224 memory-region = <&smem_region>;
230 compatible = "qcom,smsm";
232 #address-cells = <1>;
233 #size-cells = <0>;
235 qcom,ipc-1 = <&l2cc 8 4>;
236 qcom,ipc-2 = <&l2cc 8 14>;
237 qcom,ipc-3 = <&l2cc 8 23>;
238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
242 #qcom,smem-state-cells = <1>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
280 compatible = "qcom,scm-apq8064", "qcom,scm";
283 clock-names = "core";
288 #address-cells = <1>;
289 #size-cells = <1>;
291 compatible = "simple-bus";
294 compatible = "qcom,apq8064-pinctrl";
297 gpio-controller;
298 gpio-ranges = <&tlmm_pinmux 0 0 90>;
299 #gpio-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&ps_hold>;
313 intc: interrupt-controller@2000000 {
314 compatible = "qcom,msm-qgic2";
315 interrupt-controller;
316 #interrupt-cells = <3>;
322 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
323 "qcom,msm-timer";
328 clock-frequency = <27000000>;
329 cpu-offset = <0x80000>;
332 acc0: clock-controller@2088000 {
333 compatible = "qcom,kpss-acc-v1";
336 clock-names = "pll8_vote", "pxo";
337 clock-output-names = "acpu0_aux";
338 #clock-cells = <0>;
341 acc1: clock-controller@2098000 {
342 compatible = "qcom,kpss-acc-v1";
345 clock-names = "pll8_vote", "pxo";
346 clock-output-names = "acpu1_aux";
347 #clock-cells = <0>;
350 acc2: clock-controller@20a8000 {
351 compatible = "qcom,kpss-acc-v1";
354 clock-names = "pll8_vote", "pxo";
355 clock-output-names = "acpu2_aux";
356 #clock-cells = <0>;
359 acc3: clock-controller@20b8000 {
360 compatible = "qcom,kpss-acc-v1";
363 clock-names = "pll8_vote", "pxo";
364 clock-output-names = "acpu3_aux";
365 #clock-cells = <0>;
368 saw0: power-controller@2089000 {
369 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
374 saw1: power-controller@2099000 {
375 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
380 saw2: power-controller@20a9000 {
381 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
386 saw3: power-controller@20b9000 {
387 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
392 sps_sic_non_secure: sps-sic-non-secure@12100000 {
399 compatible = "qcom,gsbi-v1.0.0";
400 cell-index = <1>;
403 clock-names = "iface";
404 #address-cells = <1>;
405 #size-cells = <1>;
408 syscon-tcsr = <&tcsr>;
411 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
416 clock-names = "core", "iface";
421 compatible = "qcom,i2c-qup-v1.1.1";
422 pinctrl-0 = <&i2c1_pins>;
423 pinctrl-1 = <&i2c1_pins_sleep>;
424 pinctrl-names = "default", "sleep";
428 clock-names = "core", "iface";
429 #address-cells = <1>;
430 #size-cells = <0>;
438 compatible = "qcom,gsbi-v1.0.0";
439 cell-index = <2>;
442 clock-names = "iface";
443 #address-cells = <1>;
444 #size-cells = <1>;
447 syscon-tcsr = <&tcsr>;
450 compatible = "qcom,i2c-qup-v1.1.1";
452 pinctrl-0 = <&i2c2_pins>;
453 pinctrl-1 = <&i2c2_pins_sleep>;
454 pinctrl-names = "default", "sleep";
457 clock-names = "core", "iface";
458 #address-cells = <1>;
459 #size-cells = <0>;
466 compatible = "qcom,gsbi-v1.0.0";
467 cell-index = <3>;
470 clock-names = "iface";
471 #address-cells = <1>;
472 #size-cells = <1>;
475 compatible = "qcom,i2c-qup-v1.1.1";
476 pinctrl-0 = <&i2c3_pins>;
477 pinctrl-1 = <&i2c3_pins_sleep>;
478 pinctrl-names = "default", "sleep";
483 clock-names = "core", "iface";
484 #address-cells = <1>;
485 #size-cells = <0>;
492 compatible = "qcom,gsbi-v1.0.0";
493 cell-index = <4>;
496 clock-names = "iface";
497 #address-cells = <1>;
498 #size-cells = <1>;
502 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
506 pinctrl-0 = <&gsbi4_uart_pin_a>;
507 pinctrl-names = "default";
509 clock-names = "core", "iface";
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c4_pins>;
516 pinctrl-1 = <&i2c4_pins_sleep>;
517 pinctrl-names = "default", "sleep";
522 clock-names = "core", "iface";
529 compatible = "qcom,gsbi-v1.0.0";
530 cell-index = <5>;
533 clock-names = "iface";
534 #address-cells = <1>;
535 #size-cells = <1>;
539 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
544 clock-names = "core", "iface";
549 compatible = "qcom,spi-qup-v1.1.1";
552 pinctrl-0 = <&spi5_default>;
553 pinctrl-1 = <&spi5_sleep>;
554 pinctrl-names = "default", "sleep";
556 clock-names = "core", "iface";
558 #address-cells = <1>;
559 #size-cells = <0>;
565 compatible = "qcom,gsbi-v1.0.0";
566 cell-index = <6>;
569 clock-names = "iface";
570 #address-cells = <1>;
571 #size-cells = <1>;
575 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
580 clock-names = "core", "iface";
585 compatible = "qcom,i2c-qup-v1.1.1";
586 pinctrl-0 = <&i2c6_pins>;
587 pinctrl-1 = <&i2c6_pins_sleep>;
588 pinctrl-names = "default", "sleep";
593 clock-names = "core", "iface";
600 compatible = "qcom,gsbi-v1.0.0";
601 cell-index = <7>;
604 clock-names = "iface";
605 #address-cells = <1>;
606 #size-cells = <1>;
608 syscon-tcsr = <&tcsr>;
611 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
616 clock-names = "core", "iface";
621 compatible = "qcom,i2c-qup-v1.1.1";
622 pinctrl-0 = <&i2c7_pins>;
623 pinctrl-1 = <&i2c7_pins_sleep>;
624 pinctrl-names = "default", "sleep";
629 clock-names = "core", "iface";
635 compatible = "qcom,prng";
638 clock-names = "core";
642 compatible = "qcom,ssbi";
644 qcom,controller-type = "pmic-arbiter";
648 compatible = "qcom,ssbi";
650 qcom,controller-type = "pmic-arbiter";
654 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
656 #address-cells = <1>;
657 #size-cells = <1>;
667 gcc: clock-controller@900000 {
668 compatible = "qcom,gcc-apq8064", "syscon";
670 #clock-cells = <1>;
671 #power-domain-cells = <1>;
672 #reset-cells = <1>;
676 clock-names = "cxo", "pxo", "pll4";
678 tsens: thermal-sensor {
679 compatible = "qcom,msm8960-tsens";
681 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
682 nvmem-cell-names = "calib", "calib_backup";
684 interrupt-names = "uplow";
686 #qcom,sensors = <11>;
687 #thermal-sensor-cells = <1>;
691 lcc: clock-controller@28000000 {
692 compatible = "qcom,lcc-apq8064";
694 #clock-cells = <1>;
695 #reset-cells = <1>;
702 clock-names = "pxo",
712 mmcc: clock-controller@4000000 {
713 compatible = "qcom,mmcc-apq8064";
715 #clock-cells = <1>;
716 #power-domain-cells = <1>;
717 #reset-cells = <1>;
726 clock-names = "pxo",
736 l2cc: clock-controller@2011000 {
737 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
740 clock-names = "pll8_vote", "pxo";
741 #clock-cells = <0>;
745 compatible = "qcom,rpm-apq8064";
747 qcom,ipc = <&l2cc 0x8 2>;
752 interrupt-names = "ack", "err", "wakeup";
754 rpmcc: clock-controller {
755 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
756 #clock-cells = <1>;
758 clock-names = "pxo", "cxo";
763 compatible = "qcom,ci-hdrc";
768 clock-names = "core", "iface";
769 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
770 assigned-clock-rates = <60000000>;
772 reset-names = "core";
774 ahb-burst-config = <0>;
776 phy-names = "usb-phy";
778 #reset-cells = <1>;
782 compatible = "qcom,usb-hs-phy-apq8064",
783 "qcom,usb-hs-phy";
785 clock-names = "sleep", "ref";
787 reset-names = "por";
788 #phy-cells = <0>;
794 compatible = "qcom,ci-hdrc";
799 clock-names = "core", "iface";
800 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
801 assigned-clock-rates = <60000000>;
803 reset-names = "core";
805 ahb-burst-config = <0>;
807 phy-names = "usb-phy";
809 #reset-cells = <1>;
813 compatible = "qcom,usb-hs-phy-apq8064",
814 "qcom,usb-hs-phy";
815 #phy-cells = <0>;
817 clock-names = "sleep", "ref";
819 reset-names = "por";
825 compatible = "qcom,ci-hdrc";
830 clock-names = "core", "iface";
831 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
832 assigned-clock-rates = <60000000>;
834 reset-names = "core";
836 ahb-burst-config = <0>;
838 phy-names = "usb-phy";
840 #reset-cells = <1>;
844 compatible = "qcom,usb-hs-phy-apq8064",
845 "qcom,usb-hs-phy";
846 #phy-cells = <0>;
848 clock-names = "sleep", "ref";
850 reset-names = "por";
856 compatible = "qcom,apq8064-sata-phy";
859 reg-names = "phy_mem";
861 clock-names = "cfg";
862 #phy-cells = <0>;
866 compatible = "qcom,apq8064-ahci", "generic-ahci";
876 clock-names = "slave_iface",
882 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
884 assigned-clock-rates = <100000000>, <100000000>;
887 phy-names = "sata-phy";
888 ports-implemented = <0x1>;
893 arm,primecell-periphid = <0x00051180>;
898 clock-names = "mclk", "apb_pclk";
899 bus-width = <4>;
900 cap-sd-highspeed;
901 cap-mmc-highspeed;
902 max-frequency = <192000000>;
903 no-1-8-v;
905 dma-names = "tx", "rx";
908 sdcc3bam: dma-controller@12182000 {
909 compatible = "qcom,bam-v1.3.0";
913 clock-names = "bam_clk";
914 #dma-cells = <1>;
915 qcom,ee = <0>;
920 arm,primecell-periphid = <0x00051180>;
925 clock-names = "mclk", "apb_pclk";
926 bus-width = <4>;
927 cap-sd-highspeed;
928 cap-mmc-highspeed;
929 max-frequency = <48000000>;
931 dma-names = "tx", "rx";
932 pinctrl-names = "default";
933 pinctrl-0 = <&sdc4_gpios>;
936 sdcc4bam: dma-controller@121c2000 {
937 compatible = "qcom,bam-v1.3.0";
941 clock-names = "bam_clk";
942 #dma-cells = <1>;
943 qcom,ee = <0>;
949 pinctrl-names = "default";
950 pinctrl-0 = <&sdcc1_pins>;
951 arm,primecell-periphid = <0x00051180>;
955 clock-names = "mclk", "apb_pclk";
956 bus-width = <8>;
957 max-frequency = <96000000>;
958 non-removable;
959 cap-sd-highspeed;
960 cap-mmc-highspeed;
962 dma-names = "tx", "rx";
965 sdcc1bam: dma-controller@12402000 {
966 compatible = "qcom,bam-v1.3.0";
970 clock-names = "bam_clk";
971 #dma-cells = <1>;
972 qcom,ee = <0>;
976 compatible = "qcom,tcsr-apq8064", "syscon";
980 gpu: adreno-3xx@4300000 {
981 compatible = "qcom,adreno-320.2", "qcom,adreno";
983 reg-names = "kgsl_3d0_reg_memory";
985 interrupt-names = "kgsl_3d0_irq";
986 clock-names =
1062 operating-points-v2 = <&gpu_opp_table>;
1064 gpu_opp_table: opp-table {
1065 compatible = "operating-points-v2";
1067 opp-450000000 {
1068 opp-hz = /bits/ 64 <450000000>;
1071 opp-27000000 {
1072 opp-hz = /bits/ 64 <27000000>;
1083 compatible = "qcom,apq8064-dsi-ctrl",
1084 "qcom,mdss-dsi-ctrl";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1089 reg-names = "dsi_ctrl";
1098 clock-names = "iface", "bus", "core_mmss",
1102 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1106 assigned-clock-parents = <&dsi0_phy 0>,
1110 syscon-sfpb = <&mmss_sfpb>;
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1134 compatible = "qcom,dsi-phy-28nm-8960";
1135 #clock-cells = <1>;
1136 #phy-cells = <0>;
1141 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1142 clock-names = "iface", "ref";
1149 compatible = "qcom,mdss-dsi-ctrl";
1152 reg-names = "dsi_ctrl";
1161 clock-names = "iface",
1169 assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1173 assigned-clock-parents = <&dsi1_phy 0>,
1178 syscon-sfpb = <&mmss_sfpb>;
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1205 dsi1_phy: dsi-phy@5800200 {
1206 compatible = "qcom,dsi-phy-28nm-8960";
1210 reg-names = "dsi_pll",
1213 clock-names = "iface",
1217 #clock-cells = <1>;
1218 #phy-cells = <0>;
1224 compatible = "qcom,apq8064-iommu";
1225 #iommu-cells = <1>;
1226 clock-names =
1236 qcom,ncb = <2>;
1240 compatible = "qcom,apq8064-iommu";
1241 #iommu-cells = <1>;
1242 clock-names =
1252 qcom,ncb = <2>;
1256 compatible = "qcom,apq8064-iommu";
1257 #iommu-cells = <1>;
1258 clock-names =
1268 qcom,ncb = <3>;
1272 compatible = "qcom,apq8064-iommu";
1273 #iommu-cells = <1>;
1274 clock-names =
1284 qcom,ncb = <3>;
1288 compatible = "qcom,pcie-apq8064";
1293 reg-names = "dbi", "elbi", "parf", "config";
1295 linux,pci-domain = <0>;
1296 bus-range = <0x00 0xff>;
1297 num-lanes = <1>;
1298 #address-cells = <3>;
1299 #size-cells = <2>;
1303 interrupt-names = "msi";
1304 #interrupt-cells = <1>;
1305 interrupt-map-mask = <0 0 0 0x7>;
1306 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1313 clock-names = "core", "iface", "phy";
1319 reset-names = "axi", "ahb", "por", "pci", "phy";
1323 hdmi: hdmi-tx@4a00000 {
1324 compatible = "qcom,hdmi-tx-8960";
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&hdmi_pinctrl>;
1328 reg-names = "core_physical";
1333 clock-names = "core",
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1360 compatible = "qcom,hdmi-phy-8960";
1363 reg-names = "hdmi_phy",
1367 clock-names = "slave_iface";
1368 #phy-cells = <0>;
1369 #clock-cells = <0>;
1374 mdp: display-controller@5100000 {
1375 compatible = "qcom,mdp4";
1384 clock-names = "core_clk",
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1426 riva: riva-pil@3200800 {
1427 compatible = "qcom,riva-pil";
1430 reg-names = "ccu", "dxe", "pmu";
1432 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1434 interrupt-names = "wdog", "fatal";
1436 memory-region = <&wcnss_mem>;
1441 compatible = "qcom,wcn3660";
1444 clock-names = "xo";
1447 smd-edge {
1450 qcom,ipc = <&l2cc 8 25>;
1451 qcom,smd-edge = <6>;
1456 compatible = "qcom,wcnss";
1457 qcom,smd-channels = "WCNSS_CTRL";
1459 qcom,mmio = <&riva>;
1462 compatible = "qcom,wcnss-bt";
1466 compatible = "qcom,wcnss-wlan";
1470 interrupt-names = "tx", "rx";
1472 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1473 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1480 compatible = "arm,coresight-etb10", "arm,primecell";
1484 clock-names = "apb_pclk";
1486 in-ports {
1489 remote-endpoint = <&replicator_out0>;
1496 compatible = "arm,coresight-tpiu", "arm,primecell";
1500 clock-names = "apb_pclk";
1502 in-ports {
1505 remote-endpoint = <&replicator_out1>;
1512 compatible = "arm,coresight-static-replicator";
1515 clock-names = "apb_pclk";
1517 out-ports {
1518 #address-cells = <1>;
1519 #size-cells = <0>;
1524 remote-endpoint = <&etb_in>;
1530 remote-endpoint = <&tpiu_in>;
1535 in-ports {
1538 remote-endpoint = <&funnel_out>;
1545 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1549 clock-names = "apb_pclk";
1551 in-ports {
1552 #address-cells = <1>;
1553 #size-cells = <0>;
1557 * 2 - connected to STM component
1558 * 3 - not-connected
1559 * 6 - not-connected
1560 * 7 - not-connected
1565 remote-endpoint = <&etm0_out>;
1571 remote-endpoint = <&etm1_out>;
1577 remote-endpoint = <&etm2_out>;
1583 remote-endpoint = <&etm3_out>;
1588 out-ports {
1591 remote-endpoint = <&replicator_in>;
1598 compatible = "arm,coresight-etm3x", "arm,primecell";
1602 clock-names = "apb_pclk";
1606 out-ports {
1609 remote-endpoint = <&funnel_in0>;
1616 compatible = "arm,coresight-etm3x", "arm,primecell";
1620 clock-names = "apb_pclk";
1624 out-ports {
1627 remote-endpoint = <&funnel_in1>;
1634 compatible = "arm,coresight-etm3x", "arm,primecell";
1638 clock-names = "apb_pclk";
1642 out-ports {
1645 remote-endpoint = <&funnel_in4>;
1652 compatible = "arm,coresight-etm3x", "arm,primecell";
1656 clock-names = "apb_pclk";
1660 out-ports {
1663 remote-endpoint = <&funnel_in5>;
1670 #include "qcom-apq8064-pins.dtsi"