Lines Matching +full:1 +full:a200000
13 #address-cells = <1>;
14 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <1>;
36 #address-cells = <1>;
50 CPU1: cpu@1 {
54 reg = <1>;
219 #hwlock-cells = <1>;
232 #address-cells = <1>;
235 qcom,ipc-1 = <&l2cc 8 4>;
242 #qcom,smem-state-cells = <1>;
245 modem_smsm: modem@1 {
246 reg = <1>;
288 #address-cells = <1>;
289 #size-cells = <1>;
324 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
369 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
379 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
389 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
399 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
416 cell-index = <1>;
420 #address-cells = <1>;
421 #size-cells = <1>;
439 pinctrl-1 = <&i2c1_sleep_state>;
445 #address-cells = <1>;
459 #address-cells = <1>;
460 #size-cells = <1>;
469 pinctrl-1 = <&i2c2_sleep_state>;
474 #address-cells = <1>;
487 #address-cells = <1>;
488 #size-cells = <1>;
493 pinctrl-1 = <&i2c3_sleep_state>;
500 #address-cells = <1>;
513 #address-cells = <1>;
514 #size-cells = <1>;
532 pinctrl-1 = <&i2c4_sleep_state>;
543 gsbi5: gsbi@1a200000 {
550 #address-cells = <1>;
551 #size-cells = <1>;
554 gsbi5_serial: serial@1a240000 {
564 gsbi5_spi: spi@1a280000 {
569 pinctrl-1 = <&spi5_sleep_state>;
574 #address-cells = <1>;
586 #address-cells = <1>;
587 #size-cells = <1>;
603 pinctrl-1 = <&i2c6_sleep_state>;
621 #address-cells = <1>;
622 #size-cells = <1>;
639 pinctrl-1 = <&i2c7_sleep_state>;
650 rng@1a500000 {
672 #address-cells = <1>;
673 #size-cells = <1>;
686 #clock-cells = <1>;
687 #reset-cells = <1>;
702 #thermal-sensor-cells = <1>;
709 #clock-cells = <1>;
710 #reset-cells = <1>;
730 #clock-cells = <1>;
731 #power-domain-cells = <1>;
732 #reset-cells = <1>;
736 <&dsi0_phy 1>,
738 <&dsi1_phy 1>,
771 #clock-cells = <1>;
793 #reset-cells = <1>;
824 #reset-cells = <1>;
855 #reset-cells = <1>;
870 sata_phy0: phy@1b400000 {
917 no-1-8-v;
918 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
928 #dma-cells = <1>;
944 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
956 #dma-cells = <1>;
975 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
985 #dma-cells = <1>;
989 tcsr: syscon@1a400000 {
1012 &gfx3d 1
1044 &gfx3d1 1
1099 #address-cells = <1>;
1122 <&dsi0_phy 1>,
1123 <&dsi0_phy 1>;
1129 #address-cells = <1>;
1138 port@1 {
1139 reg = <1>;
1149 #clock-cells = <1>;
1189 <&dsi1_phy 1>,
1190 <&dsi1_phy 1>;
1195 #address-cells = <1>;
1201 #address-cells = <1>;
1210 port@1 {
1211 reg = <1>;
1231 #clock-cells = <1>;
1239 #iommu-cells = <1>;
1255 #iommu-cells = <1>;
1271 #iommu-cells = <1>;
1287 #iommu-cells = <1>;
1301 pcie: pcie@1b500000 {
1311 num-lanes = <1>;
1318 #interrupt-cells = <1>;
1320 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1366 #address-cells = <1>;
1375 port@1 {
1376 reg = <1>;
1421 #address-cells = <1>;
1430 port@1 {
1431 reg = <1>;
1503 etb@1a01000 {
1519 tpiu@1a03000 {
1542 #address-cells = <1>;
1551 port@1 {
1552 reg = <1>;
1568 funnel@1a04000 {
1576 #address-cells = <1>;
1592 port@1 {
1593 reg = <1>;
1621 etm@1a1c000 {
1639 etm@1a1d000 {
1657 etm@1a1e000 {
1675 etm@1a1f000 {