Lines Matching +full:0 +full:x124a0000
25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
174 coefficients = <1132 0>;
193 interrupts = <1 10 0x304>;
199 #clock-cells = <0>;
205 #clock-cells = <0>;
211 #clock-cells = <0>;
218 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
233 #size-cells = <0>;
238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
240 apps_smsm: apps@0 {
241 reg = <0>;
247 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
255 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
263 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
271 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
295 reg = <0x800000 0x4000>;
298 gpio-ranges = <&tlmm_pinmux 0 0 90>;
302 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
305 pinctrl-0 = <&ps_hold>;
310 reg = <0x01200000 0x8000>;
317 reg = <0x02000000 0x1000>,
318 <0x02002000 0x1000>;
324 interrupts = <1 1 0x301>,
325 <1 2 0x301>,
326 <1 3 0x301>;
327 reg = <0x0200a000 0x100>;
329 cpu-offset = <0x80000>;
334 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
338 #clock-cells = <0>;
343 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
347 #clock-cells = <0>;
352 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
356 #clock-cells = <0>;
361 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
365 #clock-cells = <0>;
370 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
376 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
382 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
388 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
394 reg = <0x12100000 0x10000>;
401 reg = <0x12440000 0x100>;
412 reg = <0x12450000 0x100>,
413 <0x12400000 0x03>;
414 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
422 pinctrl-0 = <&i2c1_pins>;
425 reg = <0x12460000 0x1000>;
426 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
430 #size-cells = <0>;
440 reg = <0x12480000 0x100>;
451 reg = <0x124a0000 0x1000>;
452 pinctrl-0 = <&i2c2_pins>;
455 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
459 #size-cells = <0>;
468 reg = <0x16200000 0x100>;
476 pinctrl-0 = <&i2c3_pins>;
479 reg = <0x16280000 0x1000>;
485 #size-cells = <0>;
494 reg = <0x16300000 0x03>;
503 reg = <0x16340000 0x100>,
504 <0x16300000 0x3>;
506 pinctrl-0 = <&gsbi4_uart_pin_a>;
515 pinctrl-0 = <&i2c4_pins>;
518 reg = <0x16380000 0x1000>;
531 reg = <0x1a200000 0x03>;
540 reg = <0x1a240000 0x100>,
541 <0x1a200000 0x03>;
542 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
550 reg = <0x1a280000 0x1000>;
551 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
552 pinctrl-0 = <&spi5_default>;
559 #size-cells = <0>;
567 reg = <0x16500000 0x03>;
576 reg = <0x16540000 0x100>,
577 <0x16500000 0x03>;
578 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
586 pinctrl-0 = <&i2c6_pins>;
589 reg = <0x16580000 0x1000>;
602 reg = <0x16600000 0x100>;
612 reg = <0x16640000 0x1000>,
613 <0x16600000 0x1000>;
614 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
622 pinctrl-0 = <&i2c7_pins>;
625 reg = <0x16680000 0x1000>;
636 reg = <0x1a500000 0x200>;
643 reg = <0x00c00000 0x1000>;
649 reg = <0x00500000 0x1000>;
655 reg = <0x00700000 0x1000>;
660 reg = <0x404 0x10>;
663 reg = <0x414 0x10>;
669 reg = <0x00900000 0x4000>;
693 reg = <0x28000000 0x1000>;
698 <0>,
699 <0>, <0>,
700 <0>, <0>,
701 <0>;
714 reg = <0x4000000 0x1000>;
722 <&dsi0_phy 0>,
724 <&dsi1_phy 0>,
738 reg = <0x2011000 0x1000>;
741 #clock-cells = <0>;
746 reg = <0x108000 0x1000>;
747 qcom,ipc = <&l2cc 0x8 2>;
764 reg = <0x12500000 0x200>,
765 <0x12500200 0x200>;
774 ahb-burst-config = <0>;
786 resets = <&usb1 0>;
788 #phy-cells = <0>;
795 reg = <0x12520000 0x200>,
796 <0x12520200 0x200>;
805 ahb-burst-config = <0>;
815 #phy-cells = <0>;
818 resets = <&usb3 0>;
826 reg = <0x12530000 0x200>,
827 <0x12530200 0x200>;
836 ahb-burst-config = <0>;
846 #phy-cells = <0>;
849 resets = <&usb4 0>;
858 reg = <0x1b400000 0x200>;
862 #phy-cells = <0>;
868 reg = <0x29000000 0x180>;
888 ports-implemented = <0x1>;
893 arm,primecell-periphid = <0x00051180>;
895 reg = <0x12180000 0x2000>;
910 reg = <0x12182000 0x8000>;
911 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
915 qcom,ee = <0>;
920 arm,primecell-periphid = <0x00051180>;
922 reg = <0x121c0000 0x2000>;
933 pinctrl-0 = <&sdc4_gpios>;
938 reg = <0x121c2000 0x8000>;
939 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
943 qcom,ee = <0>;
950 pinctrl-0 = <&sdcc1_pins>;
951 arm,primecell-periphid = <0x00051180>;
952 reg = <0x12400000 0x2000>;
967 reg = <0x12402000 0x8000>;
968 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
972 qcom,ee = <0>;
977 reg = <0x1a400000 0x100>;
982 reg = <0x04300000 0x20000>;
997 iommus = <&gfx3d 0
1029 &gfx3d1 0
1079 reg = <0x5700000 0x70>;
1086 #size-cells = <0>;
1088 reg = <0x04700000 0x200>;
1106 assigned-clock-parents = <&dsi0_phy 0>,
1107 <&dsi0_phy 0>,
1116 #size-cells = <0>;
1118 port@0 {
1119 reg = <0>;
1136 #phy-cells = <0>;
1138 reg = <0x04700200 0x100>,
1139 <0x04700300 0x200>,
1140 <0x04700500 0x5c>;
1151 reg = <0x05800000 0x200>;
1173 assigned-clock-parents = <&dsi1_phy 0>,
1174 <&dsi1_phy 0>,
1182 #size-cells = <0>;
1188 #size-cells = <0>;
1190 port@0 {
1191 reg = <0>;
1207 reg = <0x05800200 0x100>,
1208 <0x05800300 0x200>,
1209 <0x05800500 0x5c>;
1218 #phy-cells = <0>;
1232 reg = <0x07500000 0x100000>;
1248 reg = <0x07600000 0x100000>;
1264 reg = <0x07c00000 0x100000>;
1280 reg = <0x07d00000 0x100000>;
1289 reg = <0x1b500000 0x1000>,
1290 <0x1b502000 0x80>,
1291 <0x1b600000 0x100>,
1292 <0x0ff00000 0x100000>;
1295 linux,pci-domain = <0>;
1296 bus-range = <0x00 0xff>;
1300 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1301 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1305 interrupt-map-mask = <0 0 0 0x7>;
1306 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1307 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1308 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1309 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1326 pinctrl-0 = <&hdmi_pinctrl>;
1327 reg = <0x04a00000 0x2f0>;
1343 #size-cells = <0>;
1345 port@0 {
1346 reg = <0>;
1361 reg = <0x4a00400 0x60>,
1362 <0x4a00500 0x100>;
1368 #phy-cells = <0>;
1369 #clock-cells = <0>;
1376 reg = <0x05100000 0xf0000>;
1391 iommus = <&mdp_port0 0
1393 &mdp_port1 0
1398 #size-cells = <0>;
1400 port@0 {
1401 reg = <0>;
1429 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1481 reg = <0x1a01000 0x1000>;
1497 reg = <0x1a03000 0x1000>;
1519 #size-cells = <0>;
1521 port@0 {
1522 reg = <0>;
1546 reg = <0x1a04000 0x1000>;
1553 #size-cells = <0>;
1562 port@0 {
1563 reg = <0>;
1599 reg = <0x1a1c000 0x1000>;
1617 reg = <0x1a1d000 0x1000>;
1635 reg = <0x1a1e000 0x1000>;
1653 reg = <0x1a1f000 0x1000>;