Lines Matching +full:0 +full:x40027000
33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
100 reg = <0x40020000 0x4000>;
110 reg = <0x40027000 0x1000>;
114 dmas = <&edma0 0 2>, <&edma0 0 3>;
121 reg = <0x40028000 0x1000>;
125 dmas = <&edma0 0 4>, <&edma0 0 5>;
132 reg = <0x40029000 0x1000>;
136 dmas = <&edma0 0 6>, <&edma0 0 7>;
143 reg = <0x4002a000 0x1000>;
147 dmas = <&edma0 0 8>, <&edma0 0 9>;
154 #size-cells = <0>;
156 reg = <0x4002c000 0x1000>;
168 #size-cells = <0>;
170 reg = <0x4002d000 0x1000>;
182 reg = <0x4002f000 0x1000>;
186 <&clks 0>, <&clks 0>;
189 dmas = <&edma0 0 16>, <&edma0 0 17>;
195 reg = <0x40030000 0x1000>;
199 <&clks 0>, <&clks 0>;
202 dmas = <&edma0 0 18>, <&edma0 0 19>;
208 reg = <0x40031000 0x1000>;
212 <&clks 0>, <&clks 0>;
215 dmas = <&edma0 0 20>, <&edma0 0 21>;
221 reg = <0x40032000 0x1000>;
225 <&clks 0>, <&clks 0>;
234 reg = <0x40037000 0x1000>;
243 reg = <0x40038000 0x1000>;
256 reg = <0x40039000 0x1000>;
268 reg = <0x4003b000 0x1000>;
280 reg = <0x4003d000 0x1000>;
288 reg = <0x4003e000 0x1000>;
296 #size-cells = <0>;
298 reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
309 reg = <0x40048000 0x1000>;
314 reg = <0x40049000 0x1000 0x400ff000 0x40>;
320 gpio-ranges = <&iomuxc 0 0 32>;
325 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
331 gpio-ranges = <&iomuxc 0 32 32>;
336 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
342 gpio-ranges = <&iomuxc 0 64 32>;
347 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
353 gpio-ranges = <&iomuxc 0 96 32>;
358 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
364 gpio-ranges = <&iomuxc 0 128 7>;
369 reg = <0x40050000 0x400>;
374 reg = <0x40050800 0x400>;
383 reg = <0x40050c00 0x400>;
392 reg = <0x40058000 0x1200>;
403 #size-cells = <0>;
405 reg = <0x40066000 0x1000>;
409 dmas = <&edma0 0 50>,
410 <&edma0 0 51>;
417 #size-cells = <0>;
419 reg = <0x40067000 0x1000>;
423 dmas = <&edma0 0 52>, <&edma0 0 53>;
430 reg = <0x4006b000 0x1000>;
438 reg = <0x40034000 0x800>;
442 fsl,usbmisc = <&usbmisc0 0>;
450 reg = <0x40034800 0x200>;
457 reg = <0x4006e000 0x1000>;
466 reg = <0x40080000 0x0007f000>;
472 reg = <0x40098000 0x2000>,
473 <0x400a1000 0x1000>,
474 <0x400a2000 0x1000>;
487 reg = <0x400a5000 0x1000>;
492 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
493 reg = <0x400a7000 0x2000>;
496 compatible = "fsl,sec-v4.0-mon-rtc-lp";
498 offset = <0x34>;
507 reg = <0x400a9000 0x1000>;
516 reg = <0x400aa000 0x1000>;
525 #size-cells = <0>;
527 reg = <0x400ac000 0x1000>;
532 dmas = <&edma1 0 10>,
533 <&edma1 0 11>;
540 #size-cells = <0>;
542 reg = <0x400ad000 0x1000>;
547 dmas = <&edma1 0 12>, <&edma1 0 13>;
554 reg = <0x400bb000 0x1000>;
566 reg = <0x400b1000 0x1000>;
577 reg = <0x400b2000 0x1000>;
588 reg = <0x400b4000 0x800>;
592 fsl,usbmisc = <&usbmisc1 0>;
600 reg = <0x400b4800 0x200>;
607 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
620 #size-cells = <0>;
622 reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>;
633 reg = <0x400cc000 1000>;
642 reg = <0x400cd000 1000>;
651 reg = <0x400d0000 0x1000>;
662 reg = <0x400d1000 0x1000>;
673 reg = <0x400d4000 0x4000>;
683 #size-cells = <0>;
685 reg = <0x400e0000 0x4000>;
694 #size-cells = <0>;
696 reg = <0x400e6000 0x1000>;
708 #size-cells = <0>;
710 reg = <0x400e7000 0x1000>;
720 compatible = "fsl,sec-v4.0";
723 reg = <0x400f0000 0x9000>;
724 ranges = <0 0x400f0000 0x9000>;
729 compatible = "fsl,sec-v4.0-job-ring";
730 reg = <0x1000 0x1000>;
735 compatible = "fsl,sec-v4.0-job-ring";
736 reg = <0x2000 0x1000>;