Lines Matching +full:0 +full:x0000004a
31 #size-cells = <0>;
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
50 memory@0 {
52 reg = <0x0 0x0 0x0 0x0>;
57 #clock-cells = <0>;
80 offset = <0xb0>;
81 mask = <0x02>;
94 reg = <0x0 0x1080000 0x0 0x1000>;
103 reg = <0x0 0x1401000 0x0 0x1000>,
104 <0x0 0x1402000 0x0 0x2000>,
105 <0x0 0x1404000 0x0 0x2000>,
106 <0x0 0x1406000 0x0 0x2000>;
113 reg = <0x0 0x1570e00 0x0 0x8>;
120 reg = <0x0 0x1570e08 0x0 0x8>;
127 reg = <0x0 0x1530000 0x0 0x10000>;
134 reg = <0x0 0x1e80000 0x0 0x10000>;
141 reg = <0x0 0x1ee0000 0x0 0x1000>;
148 #size-cells = <0>;
149 reg = <0x0 0x1550000 0x0 0x10000>,
150 <0x0 0x40000000 0x0 0x20000000>;
160 reg = <0x0 0x1560000 0x0 0x10000>;
162 clock-frequency = <0>;
172 reg = <0x0 0x3200000 0x0 0x10000>,
173 <0x0 0x20220520 0x0 0x4>;
183 reg = <0x0 0x1570000 0x0 0x10000>;
187 ranges = <0x0 0x0 0x1570000 0x10000>;
192 #address-cells = <0>;
194 reg = <0x1ac 4>;
196 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
197 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
198 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
199 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
200 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
201 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-map-mask = <0x7 0x0>;
207 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
211 reg = <0x0 0x1700000 0x0 0x100000>;
212 ranges = <0x0 0x0 0x1700000 0x100000>;
217 compatible = "fsl,sec-v5.0-job-ring",
218 "fsl,sec-v4.0-job-ring";
219 reg = <0x10000 0x10000>;
224 compatible = "fsl,sec-v5.0-job-ring",
225 "fsl,sec-v4.0-job-ring";
226 reg = <0x20000 0x10000>;
231 compatible = "fsl,sec-v5.0-job-ring",
232 "fsl,sec-v4.0-job-ring";
233 reg = <0x30000 0x10000>;
238 compatible = "fsl,sec-v5.0-job-ring",
239 "fsl,sec-v4.0-job-ring";
240 reg = <0x40000 0x10000>;
248 reg = <0x0 0x1ee1000 0x0 0x1000>;
255 reg = <0x0 0x1f00000 0x0 0x10000>;
257 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
258 fsl,tmu-calibration = <0x00000000 0x00000020>,
259 <0x00000001 0x00000024>,
260 <0x00000002 0x0000002a>,
261 <0x00000003 0x00000032>,
262 <0x00000004 0x00000038>,
263 <0x00000005 0x0000003e>,
264 <0x00000006 0x00000043>,
265 <0x00000007 0x0000004a>,
266 <0x00000008 0x00000050>,
267 <0x00000009 0x00000059>,
268 <0x0000000a 0x0000005f>,
269 <0x0000000b 0x00000066>,
271 <0x00010000 0x00000023>,
272 <0x00010001 0x0000002b>,
273 <0x00010002 0x00000033>,
274 <0x00010003 0x0000003a>,
275 <0x00010004 0x00000042>,
276 <0x00010005 0x0000004a>,
277 <0x00010006 0x00000054>,
278 <0x00010007 0x0000005c>,
279 <0x00010008 0x00000065>,
280 <0x00010009 0x0000006f>,
282 <0x00020000 0x00000029>,
283 <0x00020001 0x00000033>,
284 <0x00020002 0x0000003d>,
285 <0x00020003 0x00000048>,
286 <0x00020004 0x00000054>,
287 <0x00020005 0x00000060>,
288 <0x00020006 0x0000006c>,
290 <0x00030000 0x00000025>,
291 <0x00030001 0x00000033>,
292 <0x00030002 0x00000043>,
293 <0x00030003 0x00000055>;
298 compatible = "fsl,ls1021a-v1.0-dspi";
300 #size-cells = <0>;
301 reg = <0x0 0x2100000 0x0 0x10000>;
311 compatible = "fsl,ls1021a-v1.0-dspi";
313 #size-cells = <0>;
314 reg = <0x0 0x2110000 0x0 0x10000>;
326 #size-cells = <0>;
327 reg = <0x0 0x2180000 0x0 0x10000>;
338 #size-cells = <0>;
339 reg = <0x0 0x2190000 0x0 0x10000>;
350 #size-cells = <0>;
351 reg = <0x0 0x21a0000 0x0 0x10000>;
361 reg = <0x0 0x21c0500 0x0 0x100>;
363 clock-frequency = <0>;
370 reg = <0x0 0x21c0600 0x0 0x100>;
372 clock-frequency = <0>;
379 reg = <0x0 0x21d0500 0x0 0x100>;
381 clock-frequency = <0>;
388 reg = <0x0 0x21d0600 0x0 0x100>;
390 clock-frequency = <0>;
397 reg = <0x0 0x29d0000 0x0 0x10000>;
404 reg = <0x0 0x29e0000 0x0 0x10000>;
411 reg = <0x0 0x29f0000 0x0 0x10000>;
418 reg = <0x0 0x2a00000 0x0 0x10000>;
425 reg = <0x0 0x2300000 0x0 0x10000>;
435 reg = <0x0 0x2310000 0x0 0x10000>;
445 reg = <0x0 0x2320000 0x0 0x10000>;
455 reg = <0x0 0x2330000 0x0 0x10000>;
465 reg = <0x0 0x2950000 0x0 0x1000>;
474 reg = <0x0 0x2960000 0x0 0x1000>;
483 reg = <0x0 0x2970000 0x0 0x1000>;
492 reg = <0x0 0x2980000 0x0 0x1000>;
501 reg = <0x0 0x2990000 0x0 0x1000>;
510 reg = <0x0 0x29a0000 0x0 0x1000>;
520 reg = <0x0 0x29d0000 0x0 0x10000>;
532 reg = <0x0 0x29e0000 0x0 0x10000>;
544 reg = <0x0 0x29f0000 0x0 0x10000>;
556 reg = <0x0 0x2a00000 0x0 0x10000>;
568 reg = <0x0 0x2a10000 0x0 0x10000>;
580 reg = <0x0 0x2a20000 0x0 0x10000>;
592 reg = <0x0 0x2a30000 0x0 0x10000>;
604 reg = <0x0 0x2a40000 0x0 0x10000>;
615 reg = <0x0 0x2ad0000 0x0 0x10000>;
623 #sound-dai-cells = <0>;
625 reg = <0x0 0x2b50000 0x0 0x10000>;
637 #sound-dai-cells = <0>;
639 reg = <0x0 0x2b60000 0x0 0x10000>;
653 reg = <0x0 0x2c00000 0x0 0x10000>,
654 <0x0 0x2c10000 0x0 0x10000>,
655 <0x0 0x2c20000 0x0 0x10000>;
668 reg = <0x0 0x2ce0000 0x0 0x10000>;
670 clocks = <&clockgen 4 0>,
671 <&clockgen 4 0>;
681 #size-cells = <0>;
682 reg = <0x0 0x2d24000 0x0 0x4000>,
683 <0x0 0x2d10030 0x0 0x4>;
690 #size-cells = <0>;
691 reg = <0x0 0x2d64000 0x0 0x4000>,
692 <0x0 0x2d50030 0x0 0x4>;
697 reg = <0x0 0x2d10e00 0x0 0xb0>;
701 fsl,tmr-add = <0xaaaaaaab>;
722 reg = <0x0 0x2d10000 0x0 0x1000>;
731 reg = <0x0 0x2d14000 0x0 0x1000>;
751 reg = <0x0 0x2d50000 0x0 0x1000>;
760 reg = <0x0 0x2d54000 0x0 0x1000>;
780 reg = <0x0 0x2d90000 0x0 0x1000>;
789 reg = <0x0 0x2d94000 0x0 0x1000>;
798 reg = <0x0 0x8600000 0x0 0x1000>;
806 reg = <0x0 0x3100000 0x0 0x10000>;
809 snps,quirk-frame-length-adjustment = <0x20>;
816 reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
817 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
820 fsl,pcie-scfg = <&scfg 0>;
825 bus-range = <0x0 0xff>;
826 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
827 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
830 interrupt-map-mask = <0 0 0 7>;
831 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
832 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
833 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
834 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
840 reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
841 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
849 bus-range = <0x0 0xff>;
850 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
851 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
854 interrupt-map-mask = <0 0 0 7>;
855 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
856 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
857 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
858 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
864 reg = <0x0 0x2a70000 0x0 0x1000>;
874 reg = <0x0 0x2a80000 0x0 0x1000>;
884 reg = <0x0 0x2a90000 0x0 0x1000>;
894 reg = <0x0 0x2aa0000 0x0 0x1000>;
904 reg = <0x0 0x10000000 0x0 0x10000>;
907 ranges = <0x0 0x0 0x10000000 0x10000>;
912 reg = <0x0 0x10010000 0x0 0x10000>;
915 ranges = <0x0 0x0 0x10010000 0x10000>;
920 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
921 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
922 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
931 block-offset = <0x1000>;
940 reg = <0x0 0x1ee2140 0x0 0x8>;
942 #power-domain-cells = <0>;
947 reg = <0x0 0x29d0000 0x0 0x10000>;
949 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
960 thermal-sensors = <&tmu 0>;