Lines Matching +full:0 +full:x30340000
56 #size-cells = <0>;
63 arm,psci-suspend-param = <0x0010000>;
71 cpu0: cpu@0 {
74 reg = <0>;
94 opp-supported-hw = <0xf>, <0xf>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
116 #phy-cells = <0>;
124 #phy-cells = <0>;
143 #size-cells = <0>;
145 port@0 {
146 reg = <0>;
188 reg = <0x00900000 0x20000>;
189 ranges = <0 0x00900000 0x20000>;
197 reg = <0x30041000 0x1000>;
203 #size-cells = <0>;
205 port@0 {
206 reg = <0>;
227 reg = <0x3007c000 0x1000>;
243 reg = <0x30083000 0x1000>;
249 #size-cells = <0>;
251 port@0 {
252 reg = <0>;
278 reg = <0x30084000 0x1000>;
301 reg = <0x30086000 0x1000>;
316 reg = <0x30087000 0x1000>;
335 reg = <0x31001000 0x1000>,
336 <0x31002000 0x2000>,
337 <0x31004000 0x2000>,
338 <0x31006000 0x2000>;
345 reg = <0x30000000 0x400000>;
350 reg = <0x30200000 0x10000>;
357 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
362 reg = <0x30210000 0x10000>;
369 gpio-ranges = <&iomuxc 0 13 32>;
374 reg = <0x30220000 0x10000>;
381 gpio-ranges = <&iomuxc 0 45 29>;
386 reg = <0x30230000 0x10000>;
393 gpio-ranges = <&iomuxc 0 74 24>;
398 reg = <0x30240000 0x10000>;
405 gpio-ranges = <&iomuxc 0 98 18>;
410 reg = <0x30250000 0x10000>;
417 gpio-ranges = <&iomuxc 0 116 23>;
422 reg = <0x30260000 0x10000>;
429 gpio-ranges = <&iomuxc 0 139 16>;
434 reg = <0x30280000 0x10000>;
441 reg = <0x30290000 0x10000>;
449 reg = <0x302a0000 0x10000>;
457 reg = <0x302b0000 0x10000>;
465 reg = <0x302c0000 0x10000>;
471 reg = <0x302d0000 0x10000>;
480 reg = <0x302e0000 0x10000>;
490 reg = <0x302f0000 0x10000>;
500 reg = <0x30300000 0x10000>;
510 reg = <0x30320000 0x10000>;
518 reg = <0x30330000 0x10000>;
525 reg = <0x30340000 0x10000>;
530 mux-reg-masks = <0x14 0x00000010>;
535 mux-controls = <&mux 0>;
537 #size-cells = <0>;
540 port@0 {
541 reg = <0>;
566 reg = <0x30350000 0x10000>;
570 reg = <0x3c 0x4>;
574 reg = <0x10 0x4>;
581 reg = <0x30360000 0x10000>;
590 anatop-reg-offset = <0x210>;
596 anatop-enable-bit = <0>;
604 anatop-reg-offset = <0x220>;
607 anatop-min-bit-val = <0x14>;
610 anatop-enable-bit = <0>;
621 #thermal-sensor-cells = <0>;
626 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
627 reg = <0x30370000 0x10000>;
630 compatible = "fsl,sec-v4.0-mon-rtc-lp";
632 offset = <0x34>;
640 compatible = "fsl,sec-v4.0-pwrkey";
653 reg = <0x30380000 0x10000>;
663 reg = <0x30390000 0x10000>;
670 reg = <0x303a0000 0x10000>;
678 #size-cells = <0>;
680 pgc_mipi_phy: power-domain@0 {
681 #power-domain-cells = <0>;
682 reg = <0>;
687 #power-domain-cells = <0>;
693 #power-domain-cells = <0>;
705 reg = <0x30400000 0x400000>;
710 reg = <0x30610000 0x10000>;
720 reg = <0x30620000 0x10000>;
730 #size-cells = <0>;
732 reg = <0x30630000 0x10000>;
744 reg = <0x30640000 0x10000>;
758 reg = <0x30650000 0x10000>;
772 reg = <0x30660000 0x10000>;
783 reg = <0x30670000 0x10000>;
794 reg = <0x30680000 0x10000>;
805 reg = <0x30690000 0x10000>;
816 reg = <0x30710000 0x10000>;
831 reg = <0x30730000 0x10000>;
841 reg = <0x30750000 0x10000>;
854 #size-cells = <0>;
856 port@0 {
857 reg = <0>;
873 #size-cells = <0>;
874 reg = <0x30760000 0x400>;
881 assigned-clock-rates = <0>, <333000000>;
895 reg = <0x30800000 0x400000>;
902 reg = <0x30800000 0x100000>;
907 #size-cells = <0>;
909 reg = <0x30820000 0x10000>;
915 dmas = <&sdma 0 7 1>, <&sdma 1 7 2>;
921 #size-cells = <0>;
923 reg = <0x30830000 0x10000>;
935 #size-cells = <0>;
937 reg = <0x30840000 0x10000>;
950 reg = <0x30860000 0x10000>;
961 reg = <0x30890000 0x10000>;
972 reg = <0x30880000 0x10000>;
981 #sound-dai-cells = <0>;
983 reg = <0x308a0000 0x10000>;
991 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
996 #sound-dai-cells = <0>;
998 reg = <0x308b0000 0x10000>;
1006 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
1011 #sound-dai-cells = <0>;
1013 reg = <0x308c0000 0x10000>;
1021 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
1027 compatible = "fsl,sec-v4.0";
1030 reg = <0x30900000 0x40000>;
1031 ranges = <0 0x30900000 0x40000>;
1038 compatible = "fsl,sec-v4.0-job-ring";
1039 reg = <0x1000 0x1000>;
1044 compatible = "fsl,sec-v4.0-job-ring";
1045 reg = <0x2000 0x1000>;
1050 compatible = "fsl,sec-v4.0-job-ring";
1051 reg = <0x3000 0x1000>;
1058 reg = <0x30a00000 0x10000>;
1063 fsl,stop-mode = <&gpr 0x10 1>;
1069 reg = <0x30a10000 0x10000>;
1074 fsl,stop-mode = <&gpr 0x10 2>;
1080 #size-cells = <0>;
1082 reg = <0x30a20000 0x10000>;
1090 #size-cells = <0>;
1092 reg = <0x30a30000 0x10000>;
1100 #size-cells = <0>;
1102 reg = <0x30a40000 0x10000>;
1110 #size-cells = <0>;
1112 reg = <0x30a50000 0x10000>;
1121 reg = <0x30a60000 0x10000>;
1132 reg = <0x30a70000 0x10000>;
1143 reg = <0x30a80000 0x10000>;
1154 reg = <0x30a90000 0x10000>;
1164 reg = <0x30aa0000 0x10000>;
1173 reg = <0x30ab0000 0x10000>;
1183 reg = <0x30b10000 0x200>;
1187 fsl,usbmisc = <&usbmisc1 0>;
1194 reg = <0x30b30000 0x200>;
1198 fsl,usbmisc = <&usbmisc3 0>;
1208 reg = <0x30b10200 0x200>;
1214 reg = <0x30b30200 0x200>;
1219 reg = <0x30b40000 0x10000>;
1233 reg = <0x30b50000 0x10000>;
1247 reg = <0x30b60000 0x10000>;
1261 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1264 #size-cells = <0>;
1274 reg = <0x30bd0000 0x10000>;
1285 reg = <0x30be0000 0x10000>;
1300 fsl,stop-mode = <&gpr 0x10 3>;
1307 reg = <0x33000000 0x2000>;
1320 #size-cells = <0>;
1321 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1328 dmas = <&dma_apbh 0>;