Lines Matching +full:0 +full:x020dc000
61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
129 clock-frequency = <0>;
135 #clock-cells = <0>;
136 clock-frequency = <0>;
154 #phy-cells = <0>;
166 reg = <0x008f8000 0x4000>;
167 ranges = <0 0x008f8000 0x4000>;
175 reg = <0x00900000 0x20000>;
176 ranges = <0 0x00900000 0x20000>;
186 reg = <0x00a01000 0x1000>,
187 <0x00a00100 0x100>;
193 reg = <0x00a02000 0x1000>;
203 reg = <0x01800000 0x4000>;
214 reg = <0x01804000 0x2000>;
228 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
239 dmas = <&dma_apbh 0>;
248 reg = <0x02000000 0x100000>;
255 reg = <0x02000000 0x40000>;
260 reg = <0x02004000 0x4000>;
262 dmas = <&sdma 14 18 0>,
263 <&sdma 15 18 0>;
268 <&clks 0>, <&clks 0>, <&clks 0>,
270 <&clks 0>, <&clks 0>,
282 #size-cells = <0>;
284 reg = <0x02008000 0x4000>;
294 #size-cells = <0>;
296 reg = <0x0200c000 0x4000>;
306 #size-cells = <0>;
308 reg = <0x02010000 0x4000>;
318 #size-cells = <0>;
320 reg = <0x02014000 0x4000>;
331 reg = <0x02020000 0x4000>;
336 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
343 reg = <0x02024000 0x4000>;
352 dmas = <&sdma 23 21 0>,
353 <&sdma 24 21 0>;
359 #sound-dai-cells = <0>;
361 reg = <0x02028000 0x4000>;
366 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
373 #sound-dai-cells = <0>;
375 reg = <0x0202c000 0x4000>;
380 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
387 #sound-dai-cells = <0>;
389 reg = <0x02030000 0x4000>;
394 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
402 reg = <0x02034000 0x4000>;
405 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
408 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
409 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
429 reg = <0x02080000 0x4000>;
439 reg = <0x02084000 0x4000>;
449 reg = <0x02088000 0x4000>;
459 reg = <0x0208c000 0x4000>;
469 reg = <0x02090000 0x4000>;
474 fsl,stop-mode = <&gpr 0x10 1>;
480 reg = <0x02094000 0x4000>;
485 fsl,stop-mode = <&gpr 0x10 2>;
491 reg = <0x02098000 0x4000>;
500 reg = <0x0209c000 0x4000>;
507 gpio-ranges = <&iomuxc 0 5 26>;
512 reg = <0x020a0000 0x4000>;
519 gpio-ranges = <&iomuxc 0 31 20>;
524 reg = <0x020a4000 0x4000>;
531 gpio-ranges = <&iomuxc 0 51 29>;
536 reg = <0x020a8000 0x4000>;
543 gpio-ranges = <&iomuxc 0 80 32>;
548 reg = <0x020ac000 0x4000>;
555 gpio-ranges = <&iomuxc 0 112 24>;
560 reg = <0x020b0000 0x4000>;
567 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
572 reg = <0x020b4000 0x4000>;
579 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
584 reg = <0x020b8000 0x4000>;
592 reg = <0x020bc000 0x4000>;
599 reg = <0x020c0000 0x4000>;
607 reg = <0x020c4000 0x4000>;
618 reg = <0x020c8000 0x1000>;
629 anatop-reg-offset = <0x110>;
635 anatop-enable-bit = <0>;
644 anatop-reg-offset = <0x120>;
647 anatop-min-bit-val = <0>;
650 anatop-enable-bit = <0>;
659 anatop-reg-offset = <0x130>;
662 anatop-min-bit-val = <0>;
665 anatop-enable-bit = <0>;
674 anatop-reg-offset = <0x140>;
675 anatop-vol-bit-shift = <0>;
677 anatop-delay-reg-offset = <0x170>;
690 anatop-reg-offset = <0x140>;
693 anatop-delay-reg-offset = <0x170>;
707 anatop-reg-offset = <0x140>;
710 anatop-delay-reg-offset = <0x170>;
731 reg = <0x020c9000 0x1000>;
739 reg = <0x020ca000 0x1000>;
746 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
747 reg = <0x020cc000 0x4000>;
750 compatible = "fsl,sec-v4.0-mon-rtc-lp";
752 offset = <0x34>;
759 offset = <0x38>;
760 value = <0x60>;
761 mask = <0x60>;
766 compatible = "fsl,sec-v4.0-pwrkey";
776 reg = <0x020d0000 0x4000>;
781 reg = <0x020d4000 0x4000>;
787 reg = <0x020d8000 0x4000>;
795 reg = <0x020dc000 0x4000>;
805 #size-cells = <0>;
807 power-domain@0 {
808 reg = <0>;
809 #power-domain-cells = <0>;
814 #power-domain-cells = <0>;
821 #power-domain-cells = <0>;
833 #power-domain-cells = <0>;
841 reg = <0x020e0000 0x4000>;
849 reg = <0x020e4000 0x4000>;
853 reg = <0x18 0x4>;
860 #size-cells = <0>;
862 port@0 {
863 reg = <0>;
881 reg = <0x020ec000 0x4000>;
896 reg = <0x02100000 0x100000>;
900 compatible = "fsl,sec-v4.0";
903 reg = <0x2100000 0x10000>;
904 ranges = <0 0x2100000 0x10000>;
913 compatible = "fsl,sec-v4.0-job-ring";
914 reg = <0x1000 0x1000>;
919 compatible = "fsl,sec-v4.0-job-ring";
920 reg = <0x2000 0x1000>;
927 reg = <0x02184000 0x200>;
931 fsl,usbmisc = <&usbmisc 0>;
933 ahb-burst-config = <0x0>;
934 tx-burst-size-dword = <0x10>;
935 rx-burst-size-dword = <0x10>;
941 reg = <0x02184200 0x200>;
946 ahb-burst-config = <0x0>;
947 tx-burst-size-dword = <0x10>;
948 rx-burst-size-dword = <0x10>;
954 reg = <0x02184400 0x200>;
962 ahb-burst-config = <0x0>;
963 tx-burst-size-dword = <0x10>;
964 rx-burst-size-dword = <0x10>;
971 reg = <0x02184800 0x200>;
977 reg = <0x02188000 0x4000>;
990 fsl,stop-mode = <&gpr 0x10 3>;
995 reg = <0x0218c000 0x4000>;
1005 reg = <0x02190000 0x4000>;
1019 reg = <0x02194000 0x4000>;
1033 reg = <0x02198000 0x4000>;
1047 reg = <0x0219c000 0x4000>;
1059 #size-cells = <0>;
1061 reg = <0x021a0000 0x4000>;
1069 #size-cells = <0>;
1071 reg = <0x021a4000 0x4000>;
1079 #size-cells = <0>;
1081 reg = <0x021a8000 0x4000>;
1089 reg = <0x021b0000 0x4000>;
1095 reg = <0x021b4000 0x4000>;
1106 fsl,stop-mode = <&gpr 0x10 4>;
1114 reg = <0x021b8000 0x4000>;
1125 reg = <0x021bc000 0x4000>;
1129 reg = <0x10 4>;
1133 reg = <0x38 4>;
1137 reg = <0x20 4>;
1143 reg = <0x021d4000 0x4000>;
1147 <&clks 0>, <&clks 0>;
1150 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1156 reg = <0x021d8000 0x4000>;
1162 reg = <0x021dc000 0x4000>;
1166 <&clks 0>, <&clks 0>;
1169 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1175 #size-cells = <0>;
1177 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1188 #size-cells = <0>;
1190 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1202 reg = <0x021e8000 0x4000>;
1207 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1215 reg = <0x021ec000 0x4000>;
1220 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1228 reg = <0x021f0000 0x4000>;
1233 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1241 reg = <0x021f4000 0x4000>;
1246 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1253 #size-cells = <0>;
1255 reg = <0x021f8000 0x4000>;
1266 reg = <0x02200000 0x100000>;
1273 reg = <0x02240000 0x40000>;
1277 reg = <0x02214000 0x4000>;
1288 reg = <0x02218000 0x4000>;
1297 reg = <0x0221c000 0x4000>;
1308 reg = <0x02220000 0x4000>;
1329 reg = <0x02224000 0x4000>;
1340 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1352 reg = <0x02280000 0x4000>;
1363 reg = <0x02284000 0x4000>;
1374 reg = <0x02288000 0x4000>;
1382 #size-cells = <0>;
1384 reg = <0x0228c000 0x4000>;
1395 reg = <0x022a0000 0x4000>;
1400 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1407 reg = <0x022a4000 0x4000>;
1417 reg = <0x022a8000 0x4000>;
1427 reg = <0x022ac000 0x4000>;
1437 reg = <0x022b0000 0x4000>;
1448 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1453 bus-range = <0x00 0xff>;
1454 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
1455 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1460 interrupt-map-mask = <0 0 0 0x7>;
1461 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1462 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1463 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1464 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;