Lines Matching +full:0 +full:x020dc000
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
97 clock-frequency = <0>;
103 #clock-cells = <0>;
104 clock-frequency = <0>;
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
127 reg = <0x00a01000 0x1000>,
128 <0x00a00100 0x100>;
134 reg = <0x00a02000 0x1000>;
146 reg = <0x02000000 0x100000>;
153 reg = <0x02000000 0x40000>;
158 reg = <0x02004000 0x4000>;
160 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
182 reg = <0x02008000 0x4000>;
194 reg = <0x0200c000 0x4000>;
206 reg = <0x02010000 0x4000>;
218 reg = <0x02014000 0x4000>;
231 reg = <0x02018000 0x4000>;
233 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
244 reg = <0x02020000 0x4000>;
246 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
257 reg = <0x02024000 0x4000>;
259 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
269 reg = <0x02028000 0x4000>;
271 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
282 reg = <0x0202c000 0x4000>;
284 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
295 reg = <0x02030000 0x4000>;
297 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
309 reg = <0x02034000 0x4000>;
311 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
322 reg = <0x02080000 0x4000>;
332 reg = <0x02084000 0x4000>;
342 reg = <0x02088000 0x4000>;
352 reg = <0x0208c000 0x4000>;
362 reg = <0x02098000 0x4000>;
371 reg = <0x0209c000 0x4000>;
379 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
384 reg = <0x020a0000 0x4000>;
392 gpio-ranges = <&iomuxc 0 50 32>;
397 reg = <0x020a4000 0x4000>;
405 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
412 reg = <0x020a8000 0x4000>;
420 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
433 reg = <0x020ac000 0x4000>;
441 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
456 reg = <0x020b0000 0x4000>;
468 reg = <0x020b8000 0x4000>;
476 reg = <0x020bc000 0x4000>;
483 reg = <0x020c0000 0x4000>;
491 reg = <0x020c4000 0x4000>;
506 reg = <0x020c8000 0x4000>;
511 #size-cells = <0>;
515 reg = <0x20c8120>;
519 anatop-reg-offset = <0x120>;
522 anatop-min-bit-val = <0>;
525 anatop-enable-bit = <0>;
542 reg = <0x020c9000 0x1000>;
552 reg = <0x020ca000 0x1000>;
560 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
561 reg = <0x020cc000 0x4000>;
564 compatible = "fsl,sec-v4.0-mon-rtc-lp";
566 offset = <0x34>;
574 offset = <0x38>;
575 mask = <0x61>;
580 compatible = "fsl,sec-v4.0-pwrkey";
591 reg = <0x020d8000 0x4000>;
599 reg = <0x020dc000 0x4000>;
608 reg = <0x020e0000 0x4000>;
614 reg = <0x020e4000 0x4000>;
619 reg = <0x020e8000 0x4000>;
630 reg = <0x020ec000 0x4000>;
642 reg = <0x20f0000 0x4000>;
651 reg = <0x020f8000 0x4000>;
662 reg = <0x020fc000 0x4000>;
675 reg = <0x02100000 0x100000>;
681 reg = <0x02184000 0x200>;
685 fsl,usbmisc = <&usbmisc 0>;
687 ahb-burst-config = <0x0>;
688 tx-burst-size-dword = <0x10>;
689 rx-burst-size-dword = <0x10>;
696 reg = <0x02184200 0x200>;
701 ahb-burst-config = <0x0>;
702 tx-burst-size-dword = <0x10>;
703 rx-burst-size-dword = <0x10>;
711 reg = <0x02184800 0x200>;
716 reg = <0x02190000 0x4000>;
730 reg = <0x02194000 0x4000>;
744 reg = <0x02198000 0x4000>;
758 #size-cells = <0>;
760 reg = <0x021a0000 0x4000>;
768 #size-cells = <0>;
770 reg = <0x021a4000 0x4000>;
778 #size-cells = <0>;
780 reg = <0x021a8000 0x4000>;
788 reg = <0x021b0000 0x4000>;
794 reg = <0x021b4000 0x4000>;
803 reg = <0x021bc000 0x4000>;
807 reg = <0x10 4>;
811 reg = <0x38 4>;
815 reg = <0x20 4>;
821 reg = <0x021d8000 0x4000>;
828 reg = <0x021f4000 0x4000>;
830 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;