Lines Matching +full:0 +full:x020dc000
59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
108 #size-cells = <0>;
112 port@0 {
113 reg = <0>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
138 #phy-cells = <0>;
143 #phy-cells = <0>;
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
167 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
169 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
178 dmas = <&dma_apbh 0>;
184 reg = <0x00120000 0x9000>;
185 interrupts = <0 115 0x04>;
194 #size-cells = <0>;
196 port@0 {
197 reg = <0>;
216 reg = <0x00130000 0x4000>;
217 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
228 reg = <0x00134000 0x4000>;
229 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
239 reg = <0x00a00600 0x20>;
240 interrupts = <1 13 0xf01>;
249 reg = <0x00a01000 0x1000>,
250 <0x00a00100 0x100>;
256 reg = <0x00a02000 0x1000>;
257 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0x01ffc000 0x04000>,
268 <0x01f00000 0x80000>;
273 bus-range = <0x00 0xff>;
274 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
275 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
280 interrupt-map-mask = <0 0 0 0x7>;
281 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
282 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
296 reg = <0x02000000 0x100000>;
303 reg = <0x02000000 0x40000>;
308 reg = <0x02004000 0x4000>;
309 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
310 dmas = <&sdma 14 18 0>,
311 <&sdma 15 18 0>;
328 #size-cells = <0>;
330 reg = <0x02008000 0x4000>;
331 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
342 #size-cells = <0>;
344 reg = <0x0200c000 0x4000>;
345 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
356 #size-cells = <0>;
358 reg = <0x02010000 0x4000>;
359 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
370 #size-cells = <0>;
372 reg = <0x02014000 0x4000>;
373 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
384 reg = <0x02020000 0x4000>;
385 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
389 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
395 #sound-dai-cells = <0>;
397 reg = <0x02024000 0x4000>;
398 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
405 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
411 #sound-dai-cells = <0>;
414 reg = <0x02028000 0x4000>;
415 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
419 dmas = <&sdma 37 1 0>,
420 <&sdma 38 1 0>;
427 #sound-dai-cells = <0>;
430 reg = <0x0202c000 0x4000>;
431 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
435 dmas = <&sdma 41 1 0>,
436 <&sdma 42 1 0>;
443 #sound-dai-cells = <0>;
446 reg = <0x02030000 0x4000>;
447 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
451 dmas = <&sdma 45 1 0>,
452 <&sdma 46 1 0>;
460 reg = <0x02034000 0x4000>;
461 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
463 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
464 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
467 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
484 reg = <0x0203c000 0x4000>;
490 reg = <0x02040000 0x3c000>;
491 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
492 <0 3 IRQ_TYPE_LEVEL_HIGH>;
503 reg = <0x0207c000 0x4000>;
509 reg = <0x02080000 0x4000>;
510 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
520 reg = <0x02084000 0x4000>;
521 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
531 reg = <0x02088000 0x4000>;
532 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
542 reg = <0x0208c000 0x4000>;
543 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
552 reg = <0x02090000 0x4000>;
553 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
557 fsl,stop-mode = <&gpr 0x34 28>;
563 reg = <0x02094000 0x4000>;
564 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
568 fsl,stop-mode = <&gpr 0x34 29>;
574 reg = <0x02098000 0x4000>;
575 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
584 reg = <0x0209c000 0x4000>;
585 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
586 <0 67 IRQ_TYPE_LEVEL_HIGH>;
595 reg = <0x020a0000 0x4000>;
596 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
597 <0 69 IRQ_TYPE_LEVEL_HIGH>;
606 reg = <0x020a4000 0x4000>;
607 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
608 <0 71 IRQ_TYPE_LEVEL_HIGH>;
617 reg = <0x020a8000 0x4000>;
618 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
619 <0 73 IRQ_TYPE_LEVEL_HIGH>;
628 reg = <0x020ac000 0x4000>;
629 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
630 <0 75 IRQ_TYPE_LEVEL_HIGH>;
639 reg = <0x020b0000 0x4000>;
640 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
641 <0 77 IRQ_TYPE_LEVEL_HIGH>;
650 reg = <0x020b4000 0x4000>;
651 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
652 <0 79 IRQ_TYPE_LEVEL_HIGH>;
661 reg = <0x020b8000 0x4000>;
662 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
669 reg = <0x020bc000 0x4000>;
670 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
676 reg = <0x020c0000 0x4000>;
677 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
684 reg = <0x020c4000 0x4000>;
685 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
686 <0 88 IRQ_TYPE_LEVEL_HIGH>;
692 reg = <0x020c8000 0x1000>;
693 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
694 <0 54 IRQ_TYPE_LEVEL_HIGH>,
695 <0 127 IRQ_TYPE_LEVEL_HIGH>;
703 anatop-reg-offset = <0x110>;
709 anatop-enable-bit = <0>;
718 anatop-reg-offset = <0x120>;
721 anatop-min-bit-val = <0>;
724 anatop-enable-bit = <0>;
733 anatop-reg-offset = <0x130>;
736 anatop-min-bit-val = <0>;
739 anatop-enable-bit = <0>;
748 anatop-reg-offset = <0x140>;
749 anatop-vol-bit-shift = <0>;
751 anatop-delay-reg-offset = <0x170>;
765 anatop-reg-offset = <0x140>;
768 anatop-delay-reg-offset = <0x170>;
782 anatop-reg-offset = <0x140>;
785 anatop-delay-reg-offset = <0x170>;
796 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
801 #thermal-sensor-cells = <0>;
807 reg = <0x020c9000 0x1000>;
808 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
815 reg = <0x020ca000 0x1000>;
816 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
822 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
823 reg = <0x020cc000 0x4000>;
826 compatible = "fsl,sec-v4.0-mon-rtc-lp";
828 offset = <0x34>;
829 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
830 <0 20 IRQ_TYPE_LEVEL_HIGH>;
836 offset = <0x38>;
837 value = <0x60>;
838 mask = <0x60>;
843 compatible = "fsl,sec-v4.0-pwrkey";
857 reg = <0x020d0000 0x4000>;
858 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
862 reg = <0x020d4000 0x4000>;
863 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
868 reg = <0x020d8000 0x4000>;
869 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
870 <0 96 IRQ_TYPE_LEVEL_HIGH>;
876 reg = <0x020dc000 0x4000>;
879 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
886 #size-cells = <0>;
888 power-domain@0 {
889 reg = <0>;
890 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
908 reg = <0x20e0000 0x38>;
918 reg = <0x20e0000 0x4000>;
922 reg = <0x020e4000 0x4000>;
923 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
927 reg = <0x020e8000 0x4000>;
928 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
933 reg = <0x020ec000 0x4000>;
934 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
947 reg = <0x02100000 0x100000>;
951 compatible = "fsl,sec-v4.0";
954 reg = <0x2100000 0x10000>;
955 ranges = <0 0x2100000 0x10000>;
963 compatible = "fsl,sec-v4.0-job-ring";
964 reg = <0x1000 0x1000>;
969 compatible = "fsl,sec-v4.0-job-ring";
970 reg = <0x2000 0x1000>;
976 reg = <0x0217c000 0x4000>;
981 reg = <0x02184000 0x200>;
982 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
985 fsl,usbmisc = <&usbmisc 0>;
986 ahb-burst-config = <0x0>;
987 tx-burst-size-dword = <0x10>;
988 rx-burst-size-dword = <0x10>;
994 reg = <0x02184200 0x200>;
995 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
1000 ahb-burst-config = <0x0>;
1001 tx-burst-size-dword = <0x10>;
1002 rx-burst-size-dword = <0x10>;
1008 reg = <0x02184400 0x200>;
1009 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1015 ahb-burst-config = <0x0>;
1016 tx-burst-size-dword = <0x10>;
1017 rx-burst-size-dword = <0x10>;
1023 reg = <0x02184600 0x200>;
1024 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1030 ahb-burst-config = <0x0>;
1031 tx-burst-size-dword = <0x10>;
1032 rx-burst-size-dword = <0x10>;
1039 reg = <0x02184800 0x200>;
1045 reg = <0x02188000 0x4000>;
1047 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1048 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1054 fsl,stop-mode = <&gpr 0x34 27>;
1061 reg = <0x0218c000 0x4000>;
1062 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1064 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1069 reg = <0x02190000 0x4000>;
1070 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1081 reg = <0x02194000 0x4000>;
1082 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1093 reg = <0x02198000 0x4000>;
1094 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1105 reg = <0x0219c000 0x4000>;
1106 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1117 #size-cells = <0>;
1119 reg = <0x021a0000 0x4000>;
1120 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1127 #size-cells = <0>;
1129 reg = <0x021a4000 0x4000>;
1130 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1137 #size-cells = <0>;
1139 reg = <0x021a8000 0x4000>;
1140 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1146 reg = <0x021ac000 0x4000>;
1151 reg = <0x021b0000 0x4000>;
1157 reg = <0x021b4000 0x4000>;
1165 reg = <0x021b8000 0x4000>;
1166 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1174 reg = <0x021bc000 0x4000>;
1180 reg = <0x10 4>;
1184 reg = <0x38 4>;
1188 reg = <0x20 4>;
1192 reg = <0x88 6>;
1197 reg = <0x021d0000 0x4000>;
1198 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1202 reg = <0x021d4000 0x4000>;
1203 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1208 reg = <0x021d8000 0x4000>;
1214 reg = <0x021dc000 0x4000>;
1216 #size-cells = <0>;
1217 interrupts = <0 100 0x04>, <0 101 0x04>;
1226 reg = <0x021e0000 0x4000>;
1231 #size-cells = <0>;
1233 port@0 {
1234 reg = <0>;
1253 reg = <0x021e4000 0x4000>;
1254 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1260 reg = <0x021e8000 0x4000>;
1261 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1265 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1272 reg = <0x021ec000 0x4000>;
1273 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1277 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1284 reg = <0x021f0000 0x4000>;
1285 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1289 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1296 reg = <0x021f4000 0x4000>;
1297 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1301 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1309 #size-cells = <0>;
1311 reg = <0x02400000 0x400000>;
1312 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1313 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1320 ipu1_csi0: port@0 {
1321 reg = <0>;
1334 #size-cells = <0>;
1337 ipu1_di0_disp0: endpoint@0 {
1338 reg = <0>;
1364 #size-cells = <0>;
1367 ipu1_di1_disp1: endpoint@0 {
1368 reg = <0>;