Lines Matching +full:0 +full:xa4

14 		reg = <0x70000000 0x20000000>,
15 		      <0xb0000000 0x20000000>;
31 		gpio = <&gpio3 31 0>; /* PEN */
38 	pinctrl-0 = <&pinctrl_hog>;
44 				MX53_PAD_GPIO_16__GPIO7_11	0x80000000
46 				MX53_PAD_GPIO_11__GPIO4_1	0x80000000
48 				MX53_PAD_GPIO_12__GPIO4_2	0x80000000
54 				MX53_PAD_EIM_D16__ECSPI1_SCLK		0x80000000
55 				MX53_PAD_EIM_D17__ECSPI1_MISO		0x80000000
56 				MX53_PAD_EIM_D18__ECSPI1_MOSI		0x80000000
62 				MX53_PAD_FEC_MDC__FEC_MDC		0x80000000
63 				MX53_PAD_FEC_MDIO__FEC_MDIO		0x80000000
64 				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x80000000
65 				MX53_PAD_FEC_RX_ER__FEC_RX_ER		0x80000000
66 				MX53_PAD_FEC_CRS_DV__FEC_RX_DV		0x80000000
67 				MX53_PAD_FEC_RXD1__FEC_RDATA_1		0x80000000
68 				MX53_PAD_FEC_RXD0__FEC_RDATA_0		0x80000000
69 				MX53_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
70 				MX53_PAD_FEC_TXD1__FEC_TDATA_1		0x80000000
71 				MX53_PAD_FEC_TXD0__FEC_TDATA_0		0x80000000
77 				MX53_PAD_EIM_D21__I2C1_SCL		0xc0000000
78 				MX53_PAD_EIM_D28__I2C1_SDA		0xc0000000
84 				MX53_PAD_PATA_DIOW__UART1_TXD_MUX	0x1e4
85 				MX53_PAD_PATA_DMACK__UART1_RXD_MUX	0x1e4
91 				MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B	0x4
92 				MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B	0x4
93 				MX53_PAD_NANDF_CLE__EMI_NANDF_CLE	0x4
94 				MX53_PAD_NANDF_ALE__EMI_NANDF_ALE	0x4
95 				MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B	0xe0
96 				MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0	0xe0
97 				MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0	0x4
98 				MX53_PAD_PATA_DATA0__EMI_NANDF_D_0	0xa4
99 				MX53_PAD_PATA_DATA1__EMI_NANDF_D_1	0xa4
100 				MX53_PAD_PATA_DATA2__EMI_NANDF_D_2	0xa4
101 				MX53_PAD_PATA_DATA3__EMI_NANDF_D_3	0xa4
102 				MX53_PAD_PATA_DATA4__EMI_NANDF_D_4	0xa4
103 				MX53_PAD_PATA_DATA5__EMI_NANDF_D_5	0xa4
104 				MX53_PAD_PATA_DATA6__EMI_NANDF_D_6	0xa4
105 				MX53_PAD_PATA_DATA7__EMI_NANDF_D_7	0xa4
113 	pinctrl-0 = <&pinctrl_ecspi1>;
121 	pinctrl-0 = <&pinctrl_fec>;
129 	pinctrl-0 = <&pinctrl_i2c1>;
134 		reg = <0x48>;
243 	pinctrl-0 = <&pinctrl_nand>;
251 	pinctrl-0 = <&pinctrl_uart1>;