Lines Matching +full:0 +full:xa4
29 reg = <0x70000000 0x20000000>;
53 pinctrl-0 = <&pinctrl_audmux>;
59 pinctrl-0 = <&pinctrl_can1>;
75 pinctrl-0 = <&pinctrl_ecspi1>;
82 pinctrl-0 = <&pinctrl_ecspi2>;
91 pinctrl-0 = <&pinctrl_esdhc1>;
97 pinctrl-0 = <&pinctrl_fec>;
105 #size-cells = <0>;
107 phy0: ethernet-phy@0 {
108 reg = <0>;
116 pinctrl-0 = <&pinctrl_i2c1>;
122 pinctrl-0 = <&pinctrl_i2c2>;
130 reg = <0x1a>;
132 pinctrl-0 = <&pinctrl_codec>;
133 #sound-dai-cells = <0>;
138 reg = <0x68>;
145 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x1e4
146 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x1e4
147 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x1e4
148 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x1e4
154 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x1e4
155 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x1e4
161 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
167 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x1e4
168 MX53_PAD_EIM_D17__ECSPI1_MISO 0x1e4
169 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x1e4
175 MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x1e4
176 MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x1e4
177 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x1e4
183 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
184 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
185 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
186 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
187 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
188 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
189 MX53_PAD_EIM_DA14__GPIO3_14 0x1f0
195 MX53_PAD_FEC_MDC__FEC_MDC 0x1e4
196 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4
197 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4
198 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4
199 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4
200 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4
201 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4
202 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4
203 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4
204 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4
205 MX53_PAD_GPIO_1__GPIO1_1 0x1c4
211 MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
212 MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
218 MX53_PAD_KEY_ROW3__I2C2_SDA 0x400001e4
219 MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4
225 MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4
226 MX53_PAD_EIM_EB2__GPIO2_30 0x1e4
232 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
233 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
234 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
235 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
236 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
237 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
238 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
239 MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x4
240 MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x4
241 MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x4
242 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
243 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
244 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
245 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
246 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
247 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
248 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
249 MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
255 MX53_PAD_GPIO_9__PWM1_PWMO 0x5
261 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
262 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
268 MX53_PAD_EIM_D24__UART3_TXD_MUX 0x1e4
269 MX53_PAD_EIM_D25__UART3_RXD_MUX 0x1e4
275 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
276 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
283 pinctrl-0 = <&pinctrl_nand>;
292 partition@0 {
294 reg = <0x00000000 0x00100000>;
300 reg = <0x00100000 0x00100000>;
306 reg = <0x00200000 0x00100000>;
312 reg = <0x01000000 0x00a00000>;
318 reg = <0x01a00000 0x005e0000>;
323 reg = <0x02000000 0x0e000000>;
330 pinctrl-0 = <&pinctrl_pwm1>;
340 pinctrl-0 = <&pinctrl_uart1>;
346 pinctrl-0 = <&pinctrl_uart3>;
352 pinctrl-0 = <&pinctrl_uart4>;