Lines Matching +full:tegra20 +full:- +full:sclk
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
23 compatible = "mmio-sram";
25 #address-cells = <1>;
26 #size-cells = <1>;
36 compatible = "nvidia,tegra20-host1x";
40 interrupt-names = "syncpt", "host1x";
42 clock-names = "host1x";
44 reset-names = "host1x", "mc";
45 power-domains = <&pd_core>;
46 operating-points-v2 = <&host1x_dvfs_opp_table>;
48 #address-cells = <1>;
49 #size-cells = <1>;
54 compatible = "nvidia,tegra20-mpe";
59 reset-names = "mpe";
60 power-domains = <&pd_mpe>;
61 operating-points-v2 = <&mpe_dvfs_opp_table>;
66 compatible = "nvidia,tegra20-vi";
71 reset-names = "vi";
72 power-domains = <&pd_venc>;
73 operating-points-v2 = <&vi_dvfs_opp_table>;
78 compatible = "nvidia,tegra20-epp";
83 reset-names = "epp";
84 power-domains = <&pd_core>;
85 operating-points-v2 = <&epp_dvfs_opp_table>;
90 compatible = "nvidia,tegra20-isp";
95 reset-names = "isp";
96 power-domains = <&pd_venc>;
101 compatible = "nvidia,tegra20-gr2d";
106 reset-names = "2d", "mc";
107 power-domains = <&pd_core>;
108 operating-points-v2 = <&gr2d_dvfs_opp_table>;
112 compatible = "nvidia,tegra20-gr3d";
116 reset-names = "3d", "mc";
117 power-domains = <&pd_3d>;
118 operating-points-v2 = <&gr3d_dvfs_opp_table>;
122 compatible = "nvidia,tegra20-dc";
127 clock-names = "dc", "parent";
129 reset-names = "dc";
130 power-domains = <&pd_core>;
131 operating-points-v2 = <&disp1_dvfs_opp_table>;
140 interconnect-names = "wina",
142 "winb-vfilter",
152 compatible = "nvidia,tegra20-dc";
157 clock-names = "dc", "parent";
159 reset-names = "dc";
160 power-domains = <&pd_core>;
161 operating-points-v2 = <&disp2_dvfs_opp_table>;
170 interconnect-names = "wina",
172 "winb-vfilter",
182 compatible = "nvidia,tegra20-hdmi";
187 clock-names = "hdmi", "parent";
189 reset-names = "hdmi";
190 power-domains = <&pd_core>;
191 operating-points-v2 = <&hdmi_dvfs_opp_table>;
192 #sound-dai-cells = <0>;
197 compatible = "nvidia,tegra20-tvo";
201 power-domains = <&pd_core>;
202 operating-points-v2 = <&tvo_dvfs_opp_table>;
207 compatible = "nvidia,tegra20-dsi";
211 clock-names = "dsi", "parent";
213 reset-names = "dsi";
214 power-domains = <&pd_core>;
215 operating-points-v2 = <&dsi_dvfs_opp_table>;
221 compatible = "arm,cortex-a9-twd-timer";
222 interrupt-parent = <&intc>;
229 intc: interrupt-controller@50041000 {
230 compatible = "arm,cortex-a9-gic";
233 interrupt-controller;
234 #interrupt-cells = <3>;
235 interrupt-parent = <&intc>;
238 cache-controller@50043000 {
239 compatible = "arm,pl310-cache";
241 arm,data-latency = <5 5 2>;
242 arm,tag-latency = <4 4 2>;
243 cache-unified;
244 cache-level = <2>;
247 lic: interrupt-controller@60004000 {
248 compatible = "nvidia,tegra20-ictlr";
253 interrupt-controller;
254 #interrupt-cells = <3>;
255 interrupt-parent = <&intc>;
259 compatible = "nvidia,tegra20-timer";
269 compatible = "nvidia,tegra20-car";
271 #clock-cells = <1>;
272 #reset-cells = <1>;
274 sclk {
275 compatible = "nvidia,tegra20-sclk";
277 power-domains = <&pd_core>;
278 operating-points-v2 = <&sclk_dvfs_opp_table>;
282 flow-controller@60007000 {
283 compatible = "nvidia,tegra20-flowctrl";
288 compatible = "nvidia,tegra20-apbdma";
308 reset-names = "dma";
309 #dma-cells = <1>;
313 compatible = "nvidia,tegra20-ahb";
318 compatible = "nvidia,tegra20-gpio";
327 #gpio-cells = <2>;
328 gpio-controller;
329 #interrupt-cells = <2>;
330 interrupt-controller;
331 gpio-ranges = <&pinmux 0 0 224>;
335 compatible = "nvidia,tegra20-vde";
339 <0x6001c200 0x100>, /* Post-processing Engine */
345 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
349 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
351 interrupt-names = "sync-token", "bsev", "sxe";
353 reset-names = "vde", "mc";
355 power-domains = <&pd_vde>;
356 operating-points-v2 = <&vde_dvfs_opp_table>;
360 compatible = "nvidia,tegra20-pinmux";
361 reg = <0x70000014 0x10>, /* Tri-state registers */
363 <0x700000a0 0x14>, /* Pull-up/down registers */
368 compatible = "nvidia,tegra20-apbmisc";
374 compatible = "nvidia,tegra20-das";
379 compatible = "nvidia,tegra20-ac97";
384 reset-names = "ac97";
386 dma-names = "rx", "tx";
391 compatible = "nvidia,tegra20-spdif";
396 clock-names = "out", "in";
399 dma-names = "rx", "tx";
400 #sound-dai-cells = <0>;
403 assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>;
404 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
408 compatible = "nvidia,tegra20-i2s";
413 reset-names = "i2s";
415 dma-names = "rx", "tx";
420 compatible = "nvidia,tegra20-i2s";
425 reset-names = "i2s";
427 dma-names = "rx", "tx";
435 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
436 * driver, the compatible is "nvidia,tegra20-hsuart".
439 compatible = "nvidia,tegra20-uart";
441 reg-shift = <2>;
446 dma-names = "rx", "tx";
451 compatible = "nvidia,tegra20-uart";
453 reg-shift = <2>;
458 dma-names = "rx", "tx";
463 compatible = "nvidia,tegra20-uart";
465 reg-shift = <2>;
470 dma-names = "rx", "tx";
475 compatible = "nvidia,tegra20-uart";
477 reg-shift = <2>;
482 dma-names = "rx", "tx";
487 compatible = "nvidia,tegra20-uart";
489 reg-shift = <2>;
494 dma-names = "rx", "tx";
498 nand-controller@70008000 {
499 compatible = "nvidia,tegra20-nand";
501 #address-cells = <1>;
502 #size-cells = <0>;
505 clock-names = "nand";
507 reset-names = "nand";
508 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
509 assigned-clock-rates = <150000000>;
510 power-domains = <&pd_core>;
511 operating-points-v2 = <&ndflash_dvfs_opp_table>;
516 compatible = "nvidia,tegra20-gmi";
518 #address-cells = <2>;
519 #size-cells = <1>;
522 clock-names = "gmi";
524 reset-names = "gmi";
525 power-domains = <&pd_core>;
526 operating-points-v2 = <&nor_dvfs_opp_table>;
531 compatible = "nvidia,tegra20-pwm";
533 #pwm-cells = <2>;
536 reset-names = "pwm";
541 compatible = "nvidia,tegra20-i2c";
544 #address-cells = <1>;
545 #size-cells = <0>;
548 clock-names = "div-clk", "fast-clk";
550 reset-names = "i2c";
552 dma-names = "rx", "tx";
557 compatible = "nvidia,tegra20-sflash";
560 #address-cells = <1>;
561 #size-cells = <0>;
564 reset-names = "spi";
566 dma-names = "rx", "tx";
571 compatible = "nvidia,tegra20-i2c";
574 #address-cells = <1>;
575 #size-cells = <0>;
578 clock-names = "div-clk", "fast-clk";
580 reset-names = "i2c";
582 dma-names = "rx", "tx";
587 compatible = "nvidia,tegra20-i2c";
590 #address-cells = <1>;
591 #size-cells = <0>;
594 clock-names = "div-clk", "fast-clk";
596 reset-names = "i2c";
598 dma-names = "rx", "tx";
603 compatible = "nvidia,tegra20-i2c-dvc";
606 #address-cells = <1>;
607 #size-cells = <0>;
610 clock-names = "div-clk", "fast-clk";
612 reset-names = "i2c";
614 dma-names = "rx", "tx";
619 compatible = "nvidia,tegra20-slink";
622 #address-cells = <1>;
623 #size-cells = <0>;
626 reset-names = "spi";
628 dma-names = "rx", "tx";
633 compatible = "nvidia,tegra20-slink";
636 #address-cells = <1>;
637 #size-cells = <0>;
640 reset-names = "spi";
642 dma-names = "rx", "tx";
647 compatible = "nvidia,tegra20-slink";
650 #address-cells = <1>;
651 #size-cells = <0>;
654 reset-names = "spi";
656 dma-names = "rx", "tx";
661 compatible = "nvidia,tegra20-slink";
664 #address-cells = <1>;
665 #size-cells = <0>;
668 reset-names = "spi";
670 dma-names = "rx", "tx";
675 compatible = "nvidia,tegra20-rtc";
682 compatible = "nvidia,tegra20-kbc";
687 reset-names = "kbc";
692 compatible = "nvidia,tegra20-pmc";
695 clock-names = "pclk", "clk32k_in";
696 #clock-cells = <1>;
698 pd_core: core-domain {
699 #power-domain-cells = <0>;
700 operating-points-v2 = <&core_opp_table>;
710 power-domains = <&pd_core>;
711 #power-domain-cells = <0>;
718 power-domains = <&pd_core>;
719 #power-domain-cells = <0>;
726 power-domains = <&pd_core>;
727 #power-domain-cells = <0>;
739 power-domains = <&pd_core>;
740 #power-domain-cells = <0>;
745 mc: memory-controller@7000f000 {
746 compatible = "nvidia,tegra20-mc-gart";
750 clock-names = "mc";
752 #reset-cells = <1>;
753 #iommu-cells = <0>;
754 #interconnect-cells = <1>;
757 emc: memory-controller@7000f400 {
758 compatible = "nvidia,tegra20-emc";
762 power-domains = <&pd_core>;
763 #address-cells = <1>;
764 #size-cells = <0>;
765 #interconnect-cells = <0>;
767 nvidia,memory-controller = <&mc>;
768 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
772 compatible = "nvidia,tegra20-efuse";
775 clock-names = "fuse";
777 reset-names = "fuse";
781 compatible = "nvidia,tegra20-pcie";
786 reg-names = "pads", "afi", "cs";
789 interrupt-names = "intr", "msi";
791 #interrupt-cells = <1>;
792 interrupt-map-mask = <0 0 0 0>;
793 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
795 bus-range = <0x00 0xff>;
796 #address-cells = <3>;
797 #size-cells = <2>;
802 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
808 clock-names = "pex", "afi", "pll_e";
812 reset-names = "pex", "afi", "pcie_x";
813 power-domains = <&pd_core>;
814 operating-points-v2 = <&pcie_dvfs_opp_table>;
820 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
822 bus-range = <0x00 0xff>;
825 #address-cells = <3>;
826 #size-cells = <2>;
829 nvidia,num-lanes = <2>;
834 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
836 bus-range = <0x00 0xff>;
839 #address-cells = <3>;
840 #size-cells = <2>;
843 nvidia,num-lanes = <2>;
848 compatible = "nvidia,tegra20-ehci";
854 reset-names = "usb";
855 nvidia,needs-double-reset;
857 power-domains = <&pd_core>;
858 operating-points-v2 = <&usbd_dvfs_opp_table>;
862 phy1: usb-phy@c5000000 {
863 compatible = "nvidia,tegra20-usb-phy";
872 clock-names = "reg", "pll_u", "timer", "utmi-pads";
874 reset-names = "usb", "utmi-pads";
875 #phy-cells = <0>;
876 nvidia,has-legacy-mode;
877 nvidia,hssync-start-delay = <9>;
878 nvidia,idle-wait-delay = <17>;
879 nvidia,elastic-limit = <16>;
880 nvidia,term-range-adj = <6>;
881 nvidia,xcvr-setup = <9>;
882 nvidia,xcvr-lsfslew = <1>;
883 nvidia,xcvr-lsrslew = <1>;
884 nvidia,has-utmi-pad-registers;
890 compatible = "nvidia,tegra20-ehci";
896 reset-names = "usb";
898 power-domains = <&pd_core>;
899 operating-points-v2 = <&usb2_dvfs_opp_table>;
903 phy2: usb-phy@c5004000 {
904 compatible = "nvidia,tegra20-usb-phy";
911 clock-names = "reg", "pll_u", "ulpi-link";
913 reset-names = "usb", "utmi-pads";
914 #phy-cells = <0>;
920 compatible = "nvidia,tegra20-ehci";
926 reset-names = "usb";
928 power-domains = <&pd_core>;
929 operating-points-v2 = <&usb3_dvfs_opp_table>;
933 phy3: usb-phy@c5008000 {
934 compatible = "nvidia,tegra20-usb-phy";
943 clock-names = "reg", "pll_u", "timer", "utmi-pads";
945 reset-names = "usb", "utmi-pads";
946 #phy-cells = <0>;
947 nvidia,hssync-start-delay = <9>;
948 nvidia,idle-wait-delay = <17>;
949 nvidia,elastic-limit = <16>;
950 nvidia,term-range-adj = <6>;
951 nvidia,xcvr-setup = <9>;
952 nvidia,xcvr-lsfslew = <2>;
953 nvidia,xcvr-lsrslew = <2>;
959 compatible = "nvidia,tegra20-sdhci";
963 clock-names = "sdhci";
965 reset-names = "sdhci";
966 power-domains = <&pd_core>;
967 operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
972 compatible = "nvidia,tegra20-sdhci";
976 clock-names = "sdhci";
978 reset-names = "sdhci";
979 power-domains = <&pd_core>;
980 operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
985 compatible = "nvidia,tegra20-sdhci";
989 clock-names = "sdhci";
991 reset-names = "sdhci";
992 power-domains = <&pd_core>;
993 operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
998 compatible = "nvidia,tegra20-sdhci";
1002 clock-names = "sdhci";
1004 reset-names = "sdhci";
1005 power-domains = <&pd_core>;
1006 operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 compatible = "arm,cortex-a9";
1023 compatible = "arm,cortex-a9";
1030 compatible = "arm,cortex-a9-pmu";
1033 interrupt-affinity = <&{/cpus/cpu@0}>,
1037 sound-hdmi {
1038 compatible = "simple-audio-card";
1039 simple-audio-card,name = "NVIDIA Tegra20 HDMI";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1044 simple-audio-card,dai-link@0 {
1048 sound-dai = <&tegra_hdmi>;
1052 sound-dai = <&tegra_spdif>;