Lines Matching +full:tegra30 +full:- +full:hsuart
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
15 interrupt-parent = <&lic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
25 compatible = "nvidia,tegra124-pcie";
30 reg-names = "pads", "afi", "cs";
33 interrupt-names = "intr", "msi";
35 #interrupt-cells = <1>;
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
40 #address-cells = <3>;
41 #size-cells = <2>;
46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
53 clock-names = "pex", "afi", "pll_e", "cml";
57 reset-names = "pex", "afi", "pcie_x";
62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
64 bus-range = <0x00 0xff>;
67 #address-cells = <3>;
68 #size-cells = <2>;
71 nvidia,num-lanes = <2>;
76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
78 bus-range = <0x00 0xff>;
81 #address-cells = <3>;
82 #size-cells = <2>;
85 nvidia,num-lanes = <1>;
90 compatible = "nvidia,tegra124-host1x";
94 interrupt-names = "syncpt", "host1x";
96 clock-names = "host1x";
98 reset-names = "host1x", "mc";
101 #address-cells = <2>;
102 #size-cells = <2>;
107 compatible = "nvidia,tegra124-dc";
111 clock-names = "dc";
113 reset-names = "dc";
125 interconnect-names = "wina",
134 compatible = "nvidia,tegra124-dc";
138 clock-names = "dc";
140 reset-names = "dc";
150 interconnect-names = "wina",
157 compatible = "nvidia,tegra124-hdmi";
162 clock-names = "hdmi", "parent";
164 reset-names = "hdmi";
169 compatible = "nvidia,tegra124-vic";
173 clock-names = "vic";
175 reset-names = "vic";
181 compatible = "nvidia,tegra124-sor";
189 clock-names = "sor", "out", "parent", "dp", "safe";
191 reset-names = "sor";
196 compatible = "nvidia,tegra124-dpaux";
201 clock-names = "dpaux", "parent";
203 reset-names = "dpaux";
206 i2c-bus {
207 #address-cells = <1>;
208 #size-cells = <0>;
213 gic: interrupt-controller@50041000 {
214 compatible = "arm,cortex-a15-gic";
215 #interrupt-cells = <3>;
216 interrupt-controller;
223 interrupt-parent = <&gic>;
232 interrupt-names = "stall", "nonstall";
235 clock-names = "gpu", "pwr";
237 reset-names = "gpu";
244 lic: interrupt-controller@60004000 {
245 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
251 interrupt-controller;
252 #interrupt-cells = <3>;
253 interrupt-parent = <&gic>;
257 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
269 compatible = "nvidia,tegra124-car";
271 #clock-cells = <1>;
272 #reset-cells = <1>;
273 nvidia,external-memory-controller = <&emc>;
276 flow-controller@60007000 {
277 compatible = "nvidia,tegra124-flowctrl";
282 compatible = "nvidia,tegra124-actmon";
287 clock-names = "actmon", "emc";
289 reset-names = "actmon";
290 operating-points-v2 = <&emc_bw_dfs_opp_table>;
292 interconnect-names = "cpu-read";
293 #cooling-cells = <2>;
297 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
307 #gpio-cells = <2>;
308 gpio-controller;
309 #interrupt-cells = <2>;
310 interrupt-controller;
311 gpio-ranges = <&pinmux 0 0 251>;
315 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
351 reset-names = "dma";
352 #dma-cells = <1>;
356 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
362 compatible = "nvidia,tegra124-pinmux";
372 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
374 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
377 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
379 reg-shift = <2>;
384 dma-names = "rx", "tx";
389 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
391 reg-shift = <2>;
396 dma-names = "rx", "tx";
401 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
403 reg-shift = <2>;
408 dma-names = "rx", "tx";
413 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
415 reg-shift = <2>;
420 dma-names = "rx", "tx";
425 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
427 #pwm-cells = <2>;
430 reset-names = "pwm";
435 compatible = "nvidia,tegra124-i2c";
438 #address-cells = <1>;
439 #size-cells = <0>;
441 clock-names = "div-clk";
443 reset-names = "i2c";
445 dma-names = "rx", "tx";
450 compatible = "nvidia,tegra124-i2c";
453 #address-cells = <1>;
454 #size-cells = <0>;
456 clock-names = "div-clk";
458 reset-names = "i2c";
460 dma-names = "rx", "tx";
465 compatible = "nvidia,tegra124-i2c";
468 #address-cells = <1>;
469 #size-cells = <0>;
471 clock-names = "div-clk";
473 reset-names = "i2c";
475 dma-names = "rx", "tx";
480 compatible = "nvidia,tegra124-i2c";
483 #address-cells = <1>;
484 #size-cells = <0>;
486 clock-names = "div-clk";
488 reset-names = "i2c";
490 dma-names = "rx", "tx";
495 compatible = "nvidia,tegra124-i2c";
498 #address-cells = <1>;
499 #size-cells = <0>;
501 clock-names = "div-clk";
503 reset-names = "i2c";
505 dma-names = "rx", "tx";
510 compatible = "nvidia,tegra124-i2c";
513 #address-cells = <1>;
514 #size-cells = <0>;
516 clock-names = "div-clk";
518 reset-names = "i2c";
520 dma-names = "rx", "tx";
525 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
528 #address-cells = <1>;
529 #size-cells = <0>;
531 clock-names = "spi";
533 reset-names = "spi";
535 dma-names = "rx", "tx";
540 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
543 #address-cells = <1>;
544 #size-cells = <0>;
546 clock-names = "spi";
548 reset-names = "spi";
550 dma-names = "rx", "tx";
555 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
558 #address-cells = <1>;
559 #size-cells = <0>;
561 clock-names = "spi";
563 reset-names = "spi";
565 dma-names = "rx", "tx";
570 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
573 #address-cells = <1>;
574 #size-cells = <0>;
576 clock-names = "spi";
578 reset-names = "spi";
580 dma-names = "rx", "tx";
585 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
588 #address-cells = <1>;
589 #size-cells = <0>;
591 clock-names = "spi";
593 reset-names = "spi";
595 dma-names = "rx", "tx";
600 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
603 #address-cells = <1>;
604 #size-cells = <0>;
606 clock-names = "spi";
608 reset-names = "spi";
610 dma-names = "rx", "tx";
615 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
622 compatible = "nvidia,tegra124-pmc";
625 clock-names = "pclk", "clk32k_in";
626 #clock-cells = <1>;
630 compatible = "nvidia,tegra124-efuse";
633 clock-names = "fuse";
635 reset-names = "fuse";
639 compatible = "nvidia,tegra124-cec";
643 clock-names = "cec";
645 hdmi-phandle = <&hdmi>;
648 mc: memory-controller@70019000 {
649 compatible = "nvidia,tegra124-mc";
652 clock-names = "mc";
656 #iommu-cells = <1>;
657 #reset-cells = <1>;
658 #interconnect-cells = <1>;
661 emc: external-memory-controller@7001b000 {
662 compatible = "nvidia,tegra124-emc";
665 clock-names = "emc";
667 nvidia,memory-controller = <&mc>;
668 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
670 #interconnect-cells = <0>;
674 compatible = "nvidia,tegra124-ahci";
680 clock-names = "sata", "sata-oob";
684 reset-names = "sata", "sata-cold", "sata-oob";
689 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
695 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
699 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
704 compatible = "nvidia,tegra124-xusb";
708 reg-names = "hcd", "fpci", "ipfs";
724 clock-names = "xusb_host", "xusb_host_src",
731 reset-names = "xusb_host", "xusb_ss", "xusb_src";
733 nvidia,xusb-padctl = <&padctl>;
739 compatible = "nvidia,tegra124-xusb-padctl";
742 reset-names = "padctl";
749 usb2-0 {
751 #phy-cells = <0>;
754 usb2-1 {
756 #phy-cells = <0>;
759 usb2-2 {
761 #phy-cells = <0>;
770 ulpi-0 {
772 #phy-cells = <0>;
781 hsic-0 {
783 #phy-cells = <0>;
786 hsic-1 {
788 #phy-cells = <0>;
797 pcie-0 {
799 #phy-cells = <0>;
802 pcie-1 {
804 #phy-cells = <0>;
807 pcie-2 {
809 #phy-cells = <0>;
812 pcie-3 {
814 #phy-cells = <0>;
817 pcie-4 {
819 #phy-cells = <0>;
828 sata-0 {
830 #phy-cells = <0>;
837 usb2-0 {
841 usb2-1 {
845 usb2-2 {
849 ulpi-0 {
853 hsic-0 {
857 hsic-1 {
861 usb3-0 {
865 usb3-1 {
872 compatible = "nvidia,tegra124-sdhci";
876 clock-names = "sdhci";
878 reset-names = "sdhci";
883 compatible = "nvidia,tegra124-sdhci";
887 clock-names = "sdhci";
889 reset-names = "sdhci";
894 compatible = "nvidia,tegra124-sdhci";
898 clock-names = "sdhci";
900 reset-names = "sdhci";
905 compatible = "nvidia,tegra124-sdhci";
909 clock-names = "sdhci";
911 reset-names = "sdhci";
915 soctherm: thermal-sensor@700e2000 {
916 compatible = "nvidia,tegra124-soctherm";
919 reg-names = "soctherm-reg", "car-reg";
922 interrupt-names = "thermal", "edp";
925 clock-names = "tsensor", "soctherm";
927 reset-names = "soctherm";
928 #thermal-sensor-cells = <1>;
930 throttle-cfgs {
933 nvidia,cpu-throt-percent = <85>;
934 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
936 #cooling-cells = <2>;
942 compatible = "nvidia,tegra124-dfll";
946 <0 0x70110200 0 0x100>; /* Look-up table RAM */
951 clock-names = "soc", "ref", "i2c";
953 reset-names = "dvco";
954 #clock-cells = <0>;
955 clock-output-names = "dfllCPU_out";
956 nvidia,sample-rate = <12500>;
957 nvidia,droop-ctrl = <0x00000f00>;
958 nvidia,force-mode = <1>;
966 compatible = "nvidia,tegra124-ahub";
973 clock-names = "d_audio", "apbif";
995 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1009 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1014 #address-cells = <2>;
1015 #size-cells = <2>;
1018 compatible = "nvidia,tegra124-i2s";
1020 nvidia,ahub-cif-ids = <4 4>;
1023 reset-names = "i2s";
1028 compatible = "nvidia,tegra124-i2s";
1030 nvidia,ahub-cif-ids = <5 5>;
1033 reset-names = "i2s";
1038 compatible = "nvidia,tegra124-i2s";
1040 nvidia,ahub-cif-ids = <6 6>;
1043 reset-names = "i2s";
1048 compatible = "nvidia,tegra124-i2s";
1050 nvidia,ahub-cif-ids = <7 7>;
1053 reset-names = "i2s";
1058 compatible = "nvidia,tegra124-i2s";
1060 nvidia,ahub-cif-ids = <8 8>;
1063 reset-names = "i2s";
1069 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1075 reset-names = "usb";
1080 phy1: usb-phy@7d000000 {
1081 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1089 clock-names = "reg", "pll_u", "utmi-pads";
1091 reset-names = "usb", "utmi-pads";
1092 #phy-cells = <0>;
1093 nvidia,hssync-start-delay = <0>;
1094 nvidia,idle-wait-delay = <17>;
1095 nvidia,elastic-limit = <16>;
1096 nvidia,term-range-adj = <6>;
1097 nvidia,xcvr-setup = <9>;
1098 nvidia,xcvr-lsfslew = <0>;
1099 nvidia,xcvr-lsrslew = <3>;
1100 nvidia,hssquelch-level = <2>;
1101 nvidia,hsdiscon-level = <5>;
1102 nvidia,xcvr-hsslew = <12>;
1103 nvidia,has-utmi-pad-registers;
1109 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1115 reset-names = "usb";
1120 phy2: usb-phy@7d004000 {
1121 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1129 clock-names = "reg", "pll_u", "utmi-pads";
1131 reset-names = "usb", "utmi-pads";
1132 #phy-cells = <0>;
1133 nvidia,hssync-start-delay = <0>;
1134 nvidia,idle-wait-delay = <17>;
1135 nvidia,elastic-limit = <16>;
1136 nvidia,term-range-adj = <6>;
1137 nvidia,xcvr-setup = <9>;
1138 nvidia,xcvr-lsfslew = <0>;
1139 nvidia,xcvr-lsrslew = <3>;
1140 nvidia,hssquelch-level = <2>;
1141 nvidia,hsdiscon-level = <5>;
1142 nvidia,xcvr-hsslew = <12>;
1148 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1154 reset-names = "usb";
1159 phy3: usb-phy@7d008000 {
1160 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1168 clock-names = "reg", "pll_u", "utmi-pads";
1170 reset-names = "usb", "utmi-pads";
1171 #phy-cells = <0>;
1172 nvidia,hssync-start-delay = <0>;
1173 nvidia,idle-wait-delay = <17>;
1174 nvidia,elastic-limit = <16>;
1175 nvidia,term-range-adj = <6>;
1176 nvidia,xcvr-setup = <9>;
1177 nvidia,xcvr-lsfslew = <0>;
1178 nvidia,xcvr-lsrslew = <3>;
1179 nvidia,hssquelch-level = <2>;
1180 nvidia,hsdiscon-level = <5>;
1181 nvidia,xcvr-hsslew = <12>;
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1192 compatible = "arm,cortex-a15";
1200 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1202 clock-latency = <300000>;
1207 compatible = "arm,cortex-a15";
1213 compatible = "arm,cortex-a15";
1219 compatible = "arm,cortex-a15";
1225 compatible = "arm,cortex-a15-pmu";
1230 interrupt-affinity = <&{/cpus/cpu@0}>,
1236 thermal-zones {
1237 cpu-thermal {
1238 polling-delay-passive = <1000>;
1239 polling-delay = <1000>;
1241 thermal-sensors =
1245 cpu-shutdown-trip {
1250 cpu_throttle_trip: throttle-trip {
1257 cooling-maps {
1260 cooling-device = <&throttle_heavy 1 1>;
1265 mem-thermal {
1266 polling-delay-passive = <1000>;
1267 polling-delay = <1000>;
1269 thermal-sensors =
1273 mem-shutdown-trip {
1278 mem-throttle-trip {
1285 cooling-maps {
1293 gpu-thermal {
1294 polling-delay-passive = <1000>;
1295 polling-delay = <1000>;
1297 thermal-sensors =
1301 gpu-shutdown-trip {
1306 gpu_throttle_trip: throttle-trip {
1313 cooling-maps {
1316 cooling-device = <&throttle_heavy 1 1>;
1321 pllx-thermal {
1322 polling-delay-passive = <1000>;
1323 polling-delay = <1000>;
1325 thermal-sensors =
1329 pllx-shutdown-trip {
1334 pllx-throttle-trip {
1341 cooling-maps {
1351 compatible = "arm,armv7-timer";
1360 interrupt-parent = <&gic>;