Lines Matching +full:0 +full:x6001c200
17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00028000>;
48 ranges = <0x54000000 0x54000000 0x01000000>;
52 reg = <0x54140000 0x00040000>;
63 reg = <0x54180000 0x00040000>;
73 reg = <0x54200000 0x00040000>;
83 nvidia,head = <0>;
92 reg = <0x54240000 0x00040000>;
111 reg = <0x54280000 0x00040000>;
123 reg = <0x54300000 0x00040000>;
130 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
134 #size-cells = <0>;
139 reg = <0x54400000 0x00040000>;
146 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
150 #size-cells = <0>;
158 reg = <0x50041000 0x1000>,
159 <0x50042000 0x1000>,
160 <0x50044000 0x2000>,
161 <0x50046000 0x2000>;
169 reg = <0x60004000 0x100>,
170 <0x60004100 0x50>,
171 <0x60004200 0x50>,
172 <0x60004300 0x50>,
173 <0x60004400 0x50>;
181 reg = <0x60005000 0x400>;
182 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
193 reg = <0x60006000 0x1000>;
200 reg = <0x60007000 0x1000>;
205 reg = <0x6000a000 0x1400>;
246 reg = <0x6000c000 0x150>;
251 reg = <0x6000d000 0x1000>;
264 gpio-ranges = <&pinmux 0 0 246>;
269 reg = <0x6001a000 0x1000>, /* Syntax Engine */
270 <0x6001b000 0x1000>, /* Video Bitstream Engine */
271 <0x6001c000 0x100>, /* Macroblock Engine */
272 <0x6001c200 0x100>, /* Post-processing Engine */
273 <0x6001c400 0x100>, /* Motion Compensation Engine */
274 <0x6001c600 0x100>, /* Transform Engine */
275 <0x6001c800 0x100>, /* Pixel prediction block */
276 <0x6001ca00 0x100>, /* Video DMA */
277 <0x6001d800 0x400>; /* Video frame controls */
293 reg = <0x70000800 0x64>, /* Chip revision */
294 <0x70000008 0x04>; /* Strapping options */
299 reg = <0x70000868 0x148>, /* Pad control registers */
300 <0x70003000 0x40c>; /* Mux registers */
313 reg = <0x70006000 0x40>;
325 reg = <0x70006040 0x40>;
337 reg = <0x70006200 0x100>;
349 reg = <0x70006300 0x100>;
361 reg = <0x7000a000 0x100>;
371 reg = <0x7000c000 0x100>;
374 #size-cells = <0>;
386 reg = <0x7000c400 0x100>;
389 #size-cells = <0>;
401 reg = <0x7000c500 0x100>;
404 #size-cells = <0>;
416 reg = <0x7000c700 0x100>;
419 #size-cells = <0>;
431 reg = <0x7000d000 0x100>;
434 #size-cells = <0>;
446 reg = <0x7000d400 0x200>;
449 #size-cells = <0>;
461 reg = <0x7000d600 0x200>;
464 #size-cells = <0>;
476 reg = <0x7000d800 0x200>;
479 #size-cells = <0>;
491 reg = <0x7000da00 0x200>;
494 #size-cells = <0>;
506 reg = <0x7000dc00 0x200>;
509 #size-cells = <0>;
521 reg = <0x7000de00 0x200>;
524 #size-cells = <0>;
536 reg = <0x7000e000 0x100>;
543 reg = <0x7000e200 0x100>;
553 reg = <0x7000e400 0x400>;
561 reg = <0x7000f800 0x400>;
570 reg = <0x70019000 0x1000>;
582 reg = <0x70080000 0x200>,
583 <0x70080200 0x100>,
584 <0x70081000 0x200>;
625 reg = <0x70080300 0x100>;
635 reg = <0x70080400 0x100>;
645 reg = <0x70080500 0x100>;
655 reg = <0x70080600 0x100>;
665 reg = <0x70080700 0x100>;
676 reg = <0x700e3000 0x100>;
683 reg = <0x78000000 0x200>;
694 reg = <0x78000200 0x200>;
705 reg = <0x78000400 0x200>;
716 reg = <0x78000600 0x200>;
727 reg = <0x7d000000 0x4000>;
739 reg = <0x7d000000 0x4000>,
740 <0x7d000000 0x4000>;
749 #phy-cells = <0>;
750 nvidia,hssync-start-delay = <0>;
755 nvidia,xcvr-lsfslew = <0>;
761 nvidia,pmc = <&tegra_pmc 0>;
767 reg = <0x7d008000 0x4000>;
779 reg = <0x7d008000 0x4000>,
780 <0x7d000000 0x4000>;
789 #phy-cells = <0>;
790 nvidia,hssync-start-delay = <0>;
795 nvidia,xcvr-lsfslew = <0>;
806 #size-cells = <0>;
808 cpu@0 {
811 reg = <0>;