Lines Matching +full:0 +full:xf8034000
44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
80 reg = <0x00300000 0x8000>;
83 ranges = <0 0x00300000 0x8000>;
102 reg = <0xfffff000 0x200>;
108 reg = <0xffffde00 0x100>;
113 reg = <0xffffe000 0x600>,
114 <0xffffe600 0x200>;
119 reg = <0xffffe800 0x200>;
126 reg = <0xffffea00 0x200>;
131 reg = <0xfffffc00 0x200>;
140 reg = <0xfffffe00 0x10>;
146 reg = <0xfffffe10 0x10>;
152 reg = <0xfffffe30 0xf>;
159 reg = <0xfffffe50 0x4>;
161 #clock-cells = <0>;
167 #size-cells = <0>;
168 reg = <0xf8008000 0x100>;
169 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
177 #size-cells = <0>;
178 reg = <0xf800c000 0x100>;
179 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
186 reg = <0xffffec00 0x200>;
187 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
195 reg = <0xffffee00 0x200>;
196 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
206 ranges = <0xfffff400 0xfffff400 0x800>;
210 pinctrl_dbgu: dbgu-0 {
218 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
230 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
242 pinctrl_ebi_addr_nand: ebi-addr-0 {
250 pinctrl_usart0: usart0-0 {
252 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
256 pinctrl_usart0_rts: usart0_rts-0 {
261 pinctrl_usart0_cts: usart0_cts-0 {
266 pinctrl_usart0_sck: usart0_sck-0 {
273 pinctrl_usart1: usart1-0 {
279 pinctrl_usart1_rts: usart1_rts-0 {
284 pinctrl_usart1_cts: usart1_cts-0 {
289 pinctrl_usart1_sck: usart1_sck-0 {
296 pinctrl_usart2: usart2-0 {
302 pinctrl_usart2_rts: usart2_rts-0 {
304 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
307 pinctrl_usart2_cts: usart2_cts-0 {
312 pinctrl_usart2_sck: usart2_sck-0 {
319 pinctrl_uart0: uart0-0 {
327 pinctrl_uart1: uart1-0 {
335 pinctrl_nand_oe_we: nand-oe-we-0 {
337 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
341 pinctrl_nand_rb: nand-rb-0 {
346 pinctrl_nand_cs: nand-cs-0 {
353 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
360 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
369 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
376 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
385 pinctrl_ssc0_tx: ssc0_tx-0 {
392 pinctrl_ssc0_rx: ssc0_rx-0 {
401 pinctrl_spi0: spi0-0 {
410 pinctrl_spi1: spi1-0 {
419 pinctrl_i2c0: i2c0-0 {
427 pinctrl_i2c1: i2c1-0 {
429 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
435 pinctrl_i2c2: i2c2-0 {
443 pinctrl_i2c_gpio0: i2c_gpio0-0 {
451 pinctrl_i2c_gpio1: i2c_gpio1-0 {
453 <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
459 pinctrl_i2c_gpio2: i2c_gpio2-0 {
467 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
480 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
493 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
502 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
513 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
517 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
521 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
525 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
529 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
533 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
537 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
541 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
545 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
551 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
555 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
559 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
563 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
567 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
571 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
575 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
579 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
583 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
590 reg = <0xfffff400 0x200>;
601 reg = <0xfffff600 0x200>;
613 reg = <0xfffff800 0x200>;
624 reg = <0xfffffa00 0x200>;
637 reg = <0xf0010000 0x4000>;
643 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
651 reg = <0xf0008000 0x600>;
652 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
653 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
658 #size-cells = <0>;
664 reg = <0xf000c000 0x600>;
665 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
666 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
671 #size-cells = <0>;
677 reg = <0xfffff200 0x200>;
681 pinctrl-0 = <&pinctrl_dbgu>;
692 reg = <0xf801c000 0x200>;
696 pinctrl-0 = <&pinctrl_usart0>;
707 reg = <0xf8020000 0x200>;
711 pinctrl-0 = <&pinctrl_usart1>;
722 reg = <0xf8024000 0x200>;
726 pinctrl-0 = <&pinctrl_usart2>;
737 reg = <0xf8010000 0x100>;
743 #size-cells = <0>;
745 pinctrl-0 = <&pinctrl_i2c0>;
752 reg = <0xf8014000 0x100>;
758 #size-cells = <0>;
760 pinctrl-0 = <&pinctrl_i2c1>;
767 reg = <0xf8018000 0x100>;
773 #size-cells = <0>;
775 pinctrl-0 = <&pinctrl_i2c2>;
782 reg = <0xf8040000 0x200>;
786 pinctrl-0 = <&pinctrl_uart0>;
794 reg = <0xf8044000 0x200>;
798 pinctrl-0 = <&pinctrl_uart1>;
806 reg = <0xf804c000 0x100>;
807 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
812 atmel,adc-channels-used = <0xffff>;
820 #size-cells = <0>;
822 reg = <0xf0000000 0x100>;
828 pinctrl-0 = <&pinctrl_spi0>;
836 #size-cells = <0>;
838 reg = <0xf0004000 0x100>;
844 pinctrl-0 = <&pinctrl_spi1>;
852 reg = <0x00500000 0x80000
853 0xf803c000 0x400>;
854 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
862 reg = <0xfffffe40 0x10>;
873 reg = <0xfffffeb0 0x40>;
881 reg = <0xf8034000 0x300>;
891 reg = <0x00600000 0x100000>;
900 reg = <0x00700000 0x100000>;
913 reg = <0x10000000 0x60000000>;
914 ranges = <0x0 0x0 0x10000000 0x10000000
915 0x1 0x0 0x20000000 0x10000000
916 0x2 0x0 0x30000000 0x10000000
917 0x3 0x0 0x40000000 0x10000000
918 0x4 0x0 0x50000000 0x10000000
919 0x5 0x0 0x60000000 0x10000000>;
934 i2c-gpio-0 {
943 #size-cells = <0>;
945 pinctrl-0 = <&pinctrl_i2c_gpio0>;
951 gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
958 #size-cells = <0>;
960 pinctrl-0 = <&pinctrl_i2c_gpio1>;
973 #size-cells = <0>;
975 pinctrl-0 = <&pinctrl_i2c_gpio2>;