Lines Matching +full:0 +full:xf8034000
42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x10000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
72 reg = <0x00300000 0x8000>;
75 ranges = <0 0x00300000 0x8000>;
94 reg = <0xfffff000 0x200>;
100 reg = <0xffffde00 0x100>;
105 reg = <0xffffe000 0x600>,
106 <0xffffe600 0x200>;
111 reg = <0xffffe800 0x200>;
118 reg = <0xffffea00 0x200>;
123 reg = <0xfffffc00 0x200>;
132 reg = <0xfffffe00 0x10>;
138 reg = <0xfffffe30 0xf>;
145 reg = <0xfffffe10 0x10>;
151 reg = <0xfffffe50 0x4>;
153 #clock-cells = <0>;
158 reg = <0xf0008000 0x600>;
159 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
160 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
165 #size-cells = <0>;
172 #size-cells = <0>;
173 reg = <0xf8008000 0x100>;
174 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
182 #size-cells = <0>;
183 reg = <0xf800c000 0x100>;
184 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
191 reg = <0xf8038000 0x2000>;
192 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
200 #size-cells = <0>;
202 port@0 {
204 #size-cells = <0>;
205 reg = <0>;
212 pinctrl-0 = <&pinctrl_lcd_pwm>;
219 reg = <0xffffec00 0x200>;
220 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
230 ranges = <0xfffff400 0xfffff400 0x800>;
234 0xffffffff 0xffe07983 0x00000000 /* pioA */
235 0x00040000 0x00047e0f 0x00000000 /* pioB */
236 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
237 0x003fffff 0x003f8000 0x00000000 /* pioD */
242 pinctrl_dbgu: dbgu-0 {
250 pinctrl_lcd_base: lcd-base-0 {
259 pinctrl_lcd_pwm: lcd-pwm-0 {
265 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
293 pinctrl_usart0: usart0-0 {
296 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
299 pinctrl_usart0_rts: usart0_rts-0 {
304 pinctrl_usart0_cts: usart0_cts-0 {
311 pinctrl_usart1: usart1-0 {
319 pinctrl_usart2: usart2-0 {
325 pinctrl_usart2_rts: usart2_rts-0 {
327 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
330 pinctrl_usart2_cts: usart2_cts-0 {
337 pinctrl_usart3: usart3-0 {
343 pinctrl_usart3_rts: usart3_rts-0 {
348 pinctrl_usart3_cts: usart3_cts-0 {
355 pinctrl_uart0: uart0-0 {
363 pinctrl_uart1: uart1-0 {
371 pinctrl_nand_rb: nand-rb-0 {
376 pinctrl_nand_cs: nand-cs-0 {
383 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
390 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
397 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
407 pinctrl_ssc0_tx: ssc0_tx-0 {
414 pinctrl_ssc0_rx: ssc0_rx-0 {
423 pinctrl_spi0: spi0-0 {
432 pinctrl_spi1: spi1-0 {
441 pinctrl_i2c0: i2c0-0 {
449 pinctrl_i2c1: i2c1-0 {
451 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
457 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
461 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
465 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
469 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
473 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
477 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
481 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
485 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
489 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
495 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
499 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
503 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
507 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
511 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
515 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
519 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
523 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
527 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
534 reg = <0xfffff400 0x200>;
545 reg = <0xfffff600 0x200>;
556 reg = <0xfffff800 0x200>;
567 reg = <0xfffffa00 0x200>;
579 reg = <0xfffff200 0x200>;
583 pinctrl-0 = <&pinctrl_dbgu>;
591 reg = <0xf0010000 0x4000>;
593 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
594 <&dma 0 AT91_DMA_CFG_PER_ID(22)>;
597 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
605 reg = <0xf801c000 0x4000>;
609 pinctrl-0 = <&pinctrl_usart0>;
617 reg = <0xf8020000 0x4000>;
621 pinctrl-0 = <&pinctrl_usart1>;
629 reg = <0xf8024000 0x4000>;
633 pinctrl-0 = <&pinctrl_usart2>;
641 reg = <0xf8028000 0x4000>;
645 pinctrl-0 = <&pinctrl_usart3>;
653 reg = <0xf8010000 0x100>;
659 #size-cells = <0>;
661 pinctrl-0 = <&pinctrl_i2c0>;
668 reg = <0xf8014000 0x100>;
674 #size-cells = <0>;
676 pinctrl-0 = <&pinctrl_i2c1>;
683 #size-cells = <0>;
685 reg = <0xf0000000 0x100>;
691 pinctrl-0 = <&pinctrl_spi0>;
699 #size-cells = <0>;
701 reg = <0xf0004000 0x100>;
707 pinctrl-0 = <&pinctrl_spi1>;
715 reg = <0xfffffe40 0x10>;
726 reg = <0xfffffeb0 0x40>;
734 reg = <0xf8034000 0x300>;
743 reg = <0xf803c000 0x4000>;
753 reg = <0x00500000 0x00100000>;
766 reg = <0x10000000 0x60000000>;
767 ranges = <0x0 0x0 0x10000000 0x10000000
768 0x1 0x0 0x20000000 0x10000000
769 0x2 0x0 0x30000000 0x10000000
770 0x3 0x0 0x40000000 0x10000000
771 0x4 0x0 0x50000000 0x10000000
772 0x5 0x0 0x60000000 0x10000000>;
787 i2c-gpio-0 {
796 #size-cells = <0>;