Lines Matching +full:0 +full:xfffffd20
40 #size-cells = <0>;
42 cpu@0 {
45 reg = <0>;
51 reg = <0x20000000 0x08000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
70 reg = <0x00300000 0x14000>;
73 ranges = <0 0x00300000 0x14000>;
78 reg = <0x00500000 0x4000>;
81 ranges = <0 0x00500000 0x4000>;
100 reg = <0xfffff000 0x200>;
106 reg = <0xfffffc00 0x100>;
115 reg = <0xffffe200 0x200>;
120 reg = <0xffffe400 0x200>;
125 reg = <0xffffe800 0x200>;
130 reg = <0xffffea00 0x200>;
135 reg = <0xffffec00 0x200>;
140 reg = <0xfffffd30 0xf>;
148 #size-cells = <0>;
149 reg = <0xfff7c000 0x100>;
150 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
157 reg = <0xfffffd00 0x10>;
163 reg = <0xfffffd10 0x10>;
171 ranges = <0xfffff200 0xfffff200 0xa00>;
175 0xfffffffb 0xffffe07f /* pioA */
176 0x0007ffff 0x39072fff /* pioB */
177 0xffffffff 0x3ffffff8 /* pioC */
178 0xfffffbff 0xffffffff /* pioD */
179 0xffe00fff 0xfbfcff00 /* pioE */
184 pinctrl_dbgu: dbgu-0 {
192 pinctrl_usart0: usart0-0 {
198 pinctrl_usart0_rts: usart0_rts-0 {
203 pinctrl_usart0_cts: usart0_cts-0 {
210 pinctrl_usart1: usart1-0 {
212 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
216 pinctrl_usart1_rts: usart1_rts-0 {
221 pinctrl_usart1_cts: usart1_cts-0 {
228 pinctrl_usart2: usart2-0 {
234 pinctrl_usart2_rts: usart2_rts-0 {
239 pinctrl_usart2_cts: usart2_cts-0 {
246 pinctrl_nand_rb: nand-rb-0 {
251 pinctrl_nand_cs: nand-cs-0 {
258 pinctrl_macb_rmii: macb_rmii-0 {
272 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
286 pinctrl_mmc0_clk: mmc0_clk-0 {
291 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
294 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
297 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
304 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
310 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
319 pinctrl_mmc1_clk: mmc1_clk-0 {
324 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
330 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
337 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
343 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
352 pinctrl_ssc0_tx: ssc0_tx-0 {
354 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
359 pinctrl_ssc0_rx: ssc0_rx-0 {
368 pinctrl_ssc1_tx: ssc1_tx-0 {
375 pinctrl_ssc1_rx: ssc1_rx-0 {
384 pinctrl_spi0: spi0-0 {
386 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
393 pinctrl_spi1: spi1-0 {
402 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
406 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
410 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
414 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
418 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
422 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
426 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
430 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
434 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
440 pinctrl_fb: fb-0 {
476 pinctrl_ac97: ac97-0 {
478 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */
487 reg = <0xfffff200 0x200>;
498 reg = <0xfffff400 0x200>;
509 reg = <0xfffff600 0x200>;
520 reg = <0xfffff800 0x200>;
531 reg = <0xfffffa00 0x200>;
543 reg = <0xffffee00 0x200>;
547 pinctrl-0 = <&pinctrl_dbgu>;
555 reg = <0xfff8c000 0x200>;
561 pinctrl-0 = <&pinctrl_usart0>;
569 reg = <0xfff90000 0x200>;
575 pinctrl-0 = <&pinctrl_usart1>;
583 reg = <0xfff94000 0x200>;
589 pinctrl-0 = <&pinctrl_usart2>;
597 reg = <0xfff98000 0x4000>;
600 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
608 reg = <0xfff9c000 0x4000>;
611 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
619 reg = <0xfffa0000 0x4000>;
622 pinctrl-0 = <&pinctrl_ac97>;
630 reg = <0xfffbc000 0x100>;
633 pinctrl-0 = <&pinctrl_macb_rmii>;
641 reg = <0xfff78000 0x4000>;
650 reg = <0xfff88000 0x100>;
653 #size-cells = <0>;
660 reg = <0xfff80000 0x600>;
661 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
663 #size-cells = <0>;
671 reg = <0xfff84000 0x600>;
672 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
674 #size-cells = <0>;
682 reg = <0xfffffd40 0x10>;
693 #size-cells = <0>;
695 reg = <0xfffa4000 0x200>;
698 pinctrl-0 = <&pinctrl_spi0>;
706 #size-cells = <0>;
708 reg = <0xfffa8000 0x200>;
711 pinctrl-0 = <&pinctrl_spi1>;
719 reg = <0xfffb8000 0x300>;
729 reg = <0xfffac000 0x300>;
732 pinctrl-0 = <&pinctrl_can_rx_tx>;
739 reg = <0xfffffd20 0x10>;
747 reg = <0xfffffd50 0x10>;
755 reg = <0xfffffd60 0x50>;
762 reg = <0x00700000 0x1000>;
765 pinctrl-0 = <&pinctrl_fb>;
773 reg = <0x00a00000 0x100000>;
786 reg = <0x10000000 0x80000000>;
787 ranges = <0x0 0x0 0x10000000 0x10000000
788 0x1 0x0 0x20000000 0x10000000
789 0x2 0x0 0x30000000 0x10000000
790 0x3 0x0 0x40000000 0x10000000
791 0x4 0x0 0x50000000 0x10000000
792 0x5 0x0 0x60000000 0x10000000>;
811 reg = <0x80000000 0x20000000>;
812 ranges = <0x0 0x0 0x80000000 0x10000000
813 0x1 0x0 0x90000000 0x10000000>;
827 i2c-gpio-0 {
836 #size-cells = <0>;