Lines Matching +full:0 +full:xfffffd20
38 #size-cells = <0>;
40 cpu@0 {
43 reg = <0>;
49 reg = <0x20000000 0x08000000>;
55 #clock-cells = <0>;
56 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
68 reg = <0x00300000 0x28000>;
71 ranges = <0 0x00300000 0x28000>;
82 reg = <0x00500000 0x100000>;
91 reg = <0x00600000 0x1000>;
94 pinctrl-0 = <&pinctrl_fb>;
106 reg = <0x10000000 0x80000000>;
107 ranges = <0x0 0x0 0x10000000 0x10000000
108 0x1 0x0 0x20000000 0x10000000
109 0x2 0x0 0x30000000 0x10000000
110 0x3 0x0 0x40000000 0x10000000
111 0x4 0x0 0x50000000 0x10000000
112 0x5 0x0 0x60000000 0x10000000
113 0x6 0x0 0x70000000 0x10000000
114 0x7 0x0 0x80000000 0x10000000>;
136 #size-cells = <0>;
137 reg = <0xfffa0000 0x100>;
138 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
139 <18 IRQ_TYPE_LEVEL_HIGH 0>,
140 <19 IRQ_TYPE_LEVEL_HIGH 0>;
147 reg = <0xfffa4000 0x4000>;
157 reg = <0xfffa8000 0x600>;
158 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
160 pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
162 #size-cells = <0>;
171 pinctrl-0 = <&pinctrl_i2c_twi>;
172 reg = <0xfffac000 0x100>;
175 #size-cells = <0>;
182 reg = <0xfffb0000 0x200>;
188 pinctrl-0 = <&pinctrl_usart0>;
196 reg = <0xfffb4000 0x200>;
202 pinctrl-0 = <&pinctrl_usart1>;
210 reg = <0xfffb8000 0x200>;
216 pinctrl-0 = <&pinctrl_usart2>;
224 reg = <0xfffbc000 0x4000>;
227 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
235 reg = <0xfffc0000 0x4000>;
238 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
246 reg = <0xfffc4000 0x4000>;
249 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
257 #size-cells = <0>;
259 reg = <0xfffc8000 0x200>;
260 cs-gpios = <0>, <0>, <0>, <0>;
263 pinctrl-0 = <&pinctrl_spi0>;
271 #size-cells = <0>;
273 reg = <0xfffcc000 0x200>;
276 pinctrl-0 = <&pinctrl_spi1>;
284 reg = <0xffffea00 0x200>;
289 reg = <0xffffec00 0x200>;
294 reg = <0xffffee00 0x200>;
301 reg = <0xfffff000 0x200>;
307 reg = <0xfffff200 0x200>;
311 pinctrl-0 = <&pinctrl_dbgu>;
321 ranges = <0xfffff400 0xfffff400 0x600>;
325 <0xffffffff 0xfffffff7>, /* pioA */
326 <0xffffffff 0xfffffff4>, /* pioB */
327 <0xffffffff 0xffffff07>; /* pioC */
331 pinctrl_dbgu: dbgu-0 {
339 pinctrl_usart0: usart0-0 {
345 pinctrl_usart0_rts: usart0_rts-0 {
350 pinctrl_usart0_cts: usart0_cts-0 {
357 pinctrl_usart1: usart1-0 {
363 pinctrl_usart1_rts: usart1_rts-0 {
368 pinctrl_usart1_cts: usart1_cts-0 {
375 pinctrl_usart2: usart2-0 {
381 pinctrl_usart2_rts: usart2_rts-0 {
386 pinctrl_usart2_cts: usart2_cts-0 {
393 pinctrl_nand_rb: nand-rb-0 {
398 pinctrl_nand_cs: nand-cs-0 {
405 pinctrl_mmc0_clk: mmc0_clk-0 {
410 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
413 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
416 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
425 pinctrl_ssc0_tx: ssc0_tx-0 {
432 pinctrl_ssc0_rx: ssc0_rx-0 {
441 pinctrl_ssc1_tx: ssc1_tx-0 {
448 pinctrl_ssc1_rx: ssc1_rx-0 {
457 pinctrl_ssc2_tx: ssc2_tx-0 {
464 pinctrl_ssc2_rx: ssc2_rx-0 {
473 pinctrl_spi0: spi0-0 {
475 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
482 pinctrl_spi1: spi1-0 {
491 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
495 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
499 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
503 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
507 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
511 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
515 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
519 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
523 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
529 pinctrl_i2c_bitbang: i2c-0-bitbang {
534 pinctrl_i2c_twi: i2c-0-twi {
542 pinctrl_fb: fb-0 {
570 reg = <0xfffff400 0x200>;
581 reg = <0xfffff600 0x200>;
592 reg = <0xfffff800 0x200>;
604 reg = <0xfffffc00 0x100>;
613 reg = <0xfffffd00 0x10>;
619 reg = <0xfffffd10 0x10>;
625 reg = <0xfffffd30 0xf>;
632 reg = <0xfffffd20 0x10>;
640 reg = <0xfffffd40 0x10>;
648 reg = <0xfffffd50 0x10>;
654 i2c-gpio-0 {
657 pinctrl-0 = <&pinctrl_i2c_bitbang>;
664 #size-cells = <0>;