Lines Matching +full:0 +full:xfffffd20
41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
52 reg = <0x20000000 0x04000000>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 reg = <0x002ff000 0x2000>;
80 ranges = <0 0x002ff000 0x2000>;
99 reg = <0xfffff000 0x200>;
105 reg = <0xffffea00 0x200>;
110 reg = <0xffffec00 0x200>;
115 reg = <0xffffee00 0x200>;
120 reg = <0xfffffc00 0x100>;
129 reg = <0xfffffd00 0x10>;
135 reg = <0xfffffd10 0x10>;
141 reg = <0xfffffd30 0xf>;
149 #size-cells = <0>;
150 reg = <0xfffa0000 0x100>;
151 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
152 <18 IRQ_TYPE_LEVEL_HIGH 0>,
153 <19 IRQ_TYPE_LEVEL_HIGH 0>;
161 #size-cells = <0>;
162 reg = <0xfffdc000 0x100>;
163 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>,
164 <27 IRQ_TYPE_LEVEL_HIGH 0>,
165 <28 IRQ_TYPE_LEVEL_HIGH 0>;
174 ranges = <0xfffff400 0xfffff400 0x600>;
178 0xffffffff 0xffc00c3b /* pioA */
179 0xffffffff 0x7fff3ccf /* pioB */
180 0xffffffff 0x007fffff /* pioC */
185 pinctrl_dbgu: dbgu-0 {
193 pinctrl_usart0: usart0-0 {
199 pinctrl_usart0_rts: usart0_rts-0 {
204 pinctrl_usart0_cts: usart0_cts-0 {
209 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
215 pinctrl_usart0_dcd: usart0_dcd-0 {
220 pinctrl_usart0_ri: usart0_ri-0 {
227 pinctrl_usart1: usart1-0 {
233 pinctrl_usart1_rts: usart1_rts-0 {
238 pinctrl_usart1_cts: usart1_cts-0 {
245 pinctrl_usart2: usart2-0 {
251 pinctrl_usart2_rts: usart2_rts-0 {
256 pinctrl_usart2_cts: usart2_cts-0 {
263 pinctrl_usart3: usart3-0 {
269 pinctrl_usart3_rts: usart3_rts-0 {
274 pinctrl_usart3_cts: usart3_cts-0 {
281 pinctrl_uart0: uart0-0 {
289 pinctrl_uart1: uart1-0 {
297 pinctrl_nand_rb: nand-rb-0 {
302 pinctrl_nand_cs: nand-cs-0 {
309 pinctrl_macb_rmii: macb_rmii-0 {
323 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
349 pinctrl_mmc0_clk: mmc0_clk-0 {
354 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
360 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
367 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
370 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
373 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
382 pinctrl_ssc0_tx: ssc0_tx-0 {
389 pinctrl_ssc0_rx: ssc0_rx-0 {
398 pinctrl_spi0: spi0-0 {
400 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
407 pinctrl_spi1: spi1-0 {
409 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
416 pinctrl_i2c_gpio0: i2c_gpio0-0 {
424 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
428 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
432 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
436 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
440 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
444 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
448 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
452 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
456 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
462 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
466 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
470 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
474 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
475 atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
478 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
482 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
486 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
490 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
494 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
501 reg = <0xfffff400 0x200>;
512 reg = <0xfffff600 0x200>;
523 reg = <0xfffff800 0x200>;
535 reg = <0xfffff200 0x200>;
539 pinctrl-0 = <&pinctrl_dbgu>;
547 reg = <0xfffb0000 0x200>;
553 pinctrl-0 = <&pinctrl_usart0>;
561 reg = <0xfffb4000 0x200>;
567 pinctrl-0 = <&pinctrl_usart1>;
575 reg = <0xfffb8000 0x200>;
581 pinctrl-0 = <&pinctrl_usart2>;
589 reg = <0xfffd0000 0x200>;
595 pinctrl-0 = <&pinctrl_usart3>;
603 reg = <0xfffd4000 0x200>;
609 pinctrl-0 = <&pinctrl_uart0>;
617 reg = <0xfffd8000 0x200>;
623 pinctrl-0 = <&pinctrl_uart1>;
631 reg = <0xfffc4000 0x100>;
634 pinctrl-0 = <&pinctrl_macb_rmii>;
642 reg = <0xfffa4000 0x4000>;
651 reg = <0xfffac000 0x100>;
654 #size-cells = <0>;
661 reg = <0xfffa8000 0x600>;
662 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
664 #size-cells = <0>;
672 reg = <0xfffbc000 0x4000>;
675 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
683 #size-cells = <0>;
685 reg = <0xfffc8000 0x200>;
688 pinctrl-0 = <&pinctrl_spi0>;
696 #size-cells = <0>;
698 reg = <0xfffcc000 0x200>;
701 pinctrl-0 = <&pinctrl_spi1>;
709 reg = <0xfffe0000 0x100>;
710 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
714 atmel,adc-channels-used = <0xf>;
721 reg = <0xfffffd20 0x10>;
729 reg = <0xfffffd40 0x10>;
740 reg = <0xfffffd50 0x10>;
747 reg = <0x00500000 0x100000>;
760 reg = <0x10000000 0x80000000>;
761 ranges = <0x0 0x0 0x10000000 0x10000000
762 0x1 0x0 0x20000000 0x10000000
763 0x2 0x0 0x30000000 0x10000000
764 0x3 0x0 0x40000000 0x10000000
765 0x4 0x0 0x50000000 0x10000000
766 0x5 0x0 0x60000000 0x10000000
767 0x6 0x0 0x70000000 0x10000000
768 0x7 0x0 0x80000000 0x10000000>;
782 i2c_gpio0: i2c-gpio-0 {
791 #size-cells = <0>;
793 pinctrl-0 = <&pinctrl_i2c_gpio0>;