Lines Matching +full:0 +full:x1b000000
24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
108 reg = <0x10009000 0x60>;
117 reg = <0x10200a80 0x20>;
125 reg = <0x10209000 0x1000>;
132 reg = <0x1020f000 0x100>;
139 reg = <0x10210000 0x1000>;
146 reg = <0x10212000 0x100>;
151 reg = <0x10217000 0x8000>,
152 <0x10005000 0x1000>;
155 gpio-ranges = <&pio 0 0 79>;
168 reg = <0x10310000 0x1000>,
169 <0x10320000 0x1000>,
170 <0x10340000 0x2000>,
171 <0x10360000 0x2000>;
178 reg = <0x10390000 0x1000>;
179 ranges = <0 0x10390000 0x10000>;
184 reg = <0x1000 0x1000>;
190 reg = <0x4000 0x1000>;
196 reg = <0x5000 0x1000>;
201 reg = <0x9000 0x5000>;
213 reg = <0x11002000 0x400>;
224 reg = <0x11003000 0x400>;
235 reg = <0x11004000 0x400>;
245 reg = <0x11006000 0x1000>;
260 reg = <0x11007000 0x90>,
261 <0x11000100 0x80>;
270 #size-cells = <0>;
278 #size-cells = <0>;
279 reg = <0x1100a000 0x100>;
291 reg = <0x11014000 0xe0>;
296 #size-cells = <0>;
302 reg = <0x1a000000 0x1000>;
310 reg = <0x1a0c0000 0x01000>,
311 <0x1a0c3e00 0x0100>;
336 ranges = <0 0x1a0c4000 0xe00>;
339 u2port0: usb-phy@0 {
340 reg = <0 0x700>;
348 reg = <0x700 0x700>;
358 reg = <0x1a100800 0x1000>;
365 reg = <0x1a140000 0x1000>;
371 reg = <0x1a145000 0x1000>;
396 bus-range = <0x00 0xff>;
397 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
401 interrupt-map-mask = <0 0 0 7>;
402 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
403 <0 0 0 2 &pcie_intc1 1>,
404 <0 0 0 3 &pcie_intc1 2>,
405 <0 0 0 4 &pcie_intc1 3>;
408 #address-cells = <0>;
418 ranges = <0 0x1a14a000 0x1000>;
421 pcieport1: pcie-phy@0 {
422 reg = <0 0x1000>;
432 reg = <0x1b000000 0x1000>;
439 reg = <0x1b100000 0x20000>;
475 #size-cells = <0>;
481 reg = <0x1b128000 0x3000>;
487 reg = <0x1b130000 0x3000>;