Lines Matching +full:opp +full:- +full:1300000000
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
18 #include <dt-bindings/thermal/thermal.h>
22 interrupt-parent = <&sysirq>;
23 #address-cells = <2>;
24 #size-cells = <2>;
26 cpu_opp_table: opp-table {
27 compatible = "operating-points-v2";
28 opp-shared;
30 opp-98000000 {
31 opp-hz = /bits/ 64 <98000000>;
32 opp-microvolt = <1050000>;
35 opp-198000000 {
36 opp-hz = /bits/ 64 <198000000>;
37 opp-microvolt = <1050000>;
40 opp-398000000 {
41 opp-hz = /bits/ 64 <398000000>;
42 opp-microvolt = <1050000>;
45 opp-598000000 {
46 opp-hz = /bits/ 64 <598000000>;
47 opp-microvolt = <1050000>;
50 opp-747500000 {
51 opp-hz = /bits/ 64 <747500000>;
52 opp-microvolt = <1050000>;
55 opp-1040000000 {
56 opp-hz = /bits/ 64 <1040000000>;
57 opp-microvolt = <1150000>;
60 opp-1196000000 {
61 opp-hz = /bits/ 64 <1196000000>;
62 opp-microvolt = <1200000>;
65 opp-1300000000 {
66 opp-hz = /bits/ 64 <1300000000>;
67 opp-microvolt = <1300000>;
72 #address-cells = <1>;
73 #size-cells = <0>;
74 enable-method = "mediatek,mt6589-smp";
78 compatible = "arm,cortex-a7";
82 clock-names = "cpu", "intermediate";
83 operating-points-v2 = <&cpu_opp_table>;
84 #cooling-cells = <2>;
85 clock-frequency = <1300000000>;
90 compatible = "arm,cortex-a7";
94 clock-names = "cpu", "intermediate";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>;
97 clock-frequency = <1300000000>;
102 compatible = "arm,cortex-a7";
106 clock-names = "cpu", "intermediate";
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 clock-frequency = <1300000000>;
114 compatible = "arm,cortex-a7";
118 clock-names = "cpu", "intermediate";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 clock-frequency = <1300000000>;
126 compatible = "arm,cortex-a7-pmu";
131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
135 compatible = "fixed-clock";
136 clock-frequency = <13000000>;
137 #clock-cells = <0>;
140 rtc32k: oscillator-1 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <32000>;
144 clock-output-names = "rtc32k";
147 clk26m: oscillator-0 {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <26000000>;
151 clock-output-names = "clk26m";
154 thermal-zones {
155 cpu_thermal: cpu-thermal {
156 polling-delay-passive = <1000>;
157 polling-delay = <1000>;
159 thermal-sensors = <&thermal 0>;
162 cpu_passive: cpu-passive {
168 cpu_active: cpu-active {
174 cpu_hot: cpu-hot {
180 cpu-crit {
187 cooling-maps {
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
216 compatible = "arm,armv7-timer";
217 interrupt-parent = <&gic>;
222 clock-frequency = <13000000>;
223 arm,cpu-registers-not-fw-configured;
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
231 #clock-cells = <1>;
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
239 #clock-cells = <1>;
240 #reset-cells = <1>;
244 compatible = "mediatek,mt7623-pericfg",
245 "mediatek,mt2701-pericfg",
248 #clock-cells = <1>;
249 #reset-cells = <1>;
253 compatible = "mediatek,mt7623-pinctrl";
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 interrupt-controller;
259 interrupt-parent = <&gic>;
260 #interrupt-cells = <2>;
266 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
270 scpsys: power-controller@10006000 {
271 compatible = "mediatek,mt7623-scpsys",
272 "mediatek,mt2701-scpsys",
274 #power-domain-cells = <1>;
280 clock-names = "mm", "mfg", "ethif";
284 compatible = "mediatek,mt7623-wdt",
285 "mediatek,mt6589-wdt";
290 compatible = "mediatek,mt7623-timer",
291 "mediatek,mt6577-timer";
295 clock-names = "system-clk", "rtc-clk";
299 compatible = "mediatek,mt7623-pwrap",
300 "mediatek,mt2701-pwrap";
302 reg-names = "pwrap";
305 reset-names = "pwrap";
308 clock-names = "spi", "wrap";
312 compatible = "mediatek,mt7623-cir";
316 clock-names = "clk";
320 sysirq: interrupt-controller@10200100 {
321 compatible = "mediatek,mt7623-sysirq",
322 "mediatek,mt6577-sysirq";
323 interrupt-controller;
324 #interrupt-cells = <3>;
325 interrupt-parent = <&gic>;
330 compatible = "mediatek,mt7623-efuse",
331 "mediatek,mt8173-efuse";
333 #address-cells = <1>;
334 #size-cells = <1>;
341 compatible = "mediatek,mt7623-apmixedsys",
342 "mediatek,mt2701-apmixedsys",
345 #clock-cells = <1>;
349 compatible = "mediatek,mt7623-rng";
352 clock-names = "rng";
355 gic: interrupt-controller@10211000 {
356 compatible = "arm,cortex-a7-gic";
357 interrupt-controller;
358 #interrupt-cells = <3>;
359 interrupt-parent = <&gic>;
367 compatible = "mediatek,mt7623-auxadc",
368 "mediatek,mt2701-auxadc";
371 clock-names = "main";
372 #io-channel-cells = <1>;
376 compatible = "mediatek,mt7623-uart",
377 "mediatek,mt6577-uart";
382 clock-names = "baud", "bus";
387 compatible = "mediatek,mt7623-uart",
388 "mediatek,mt6577-uart";
393 clock-names = "baud", "bus";
398 compatible = "mediatek,mt7623-uart",
399 "mediatek,mt6577-uart";
404 clock-names = "baud", "bus";
409 compatible = "mediatek,mt7623-uart",
410 "mediatek,mt6577-uart";
415 clock-names = "baud", "bus";
420 compatible = "mediatek,mt7623-pwm";
422 #pwm-cells = <2>;
430 clock-names = "top", "main", "pwm1", "pwm2",
436 compatible = "mediatek,mt7623-i2c",
437 "mediatek,mt6577-i2c";
441 clock-div = <16>;
444 clock-names = "main", "dma";
445 #address-cells = <1>;
446 #size-cells = <0>;
451 compatible = "mediatek,mt7623-i2c",
452 "mediatek,mt6577-i2c";
456 clock-div = <16>;
459 clock-names = "main", "dma";
460 #address-cells = <1>;
461 #size-cells = <0>;
466 compatible = "mediatek,mt7623-i2c",
467 "mediatek,mt6577-i2c";
471 clock-div = <16>;
474 clock-names = "main", "dma";
475 #address-cells = <1>;
476 #size-cells = <0>;
481 compatible = "mediatek,mt7623-spi",
482 "mediatek,mt2701-spi";
483 #address-cells = <1>;
484 #size-cells = <0>;
490 clock-names = "parent-clk", "sel-clk", "spi-clk";
495 #thermal-sensor-cells = <1>;
496 compatible = "mediatek,mt7623-thermal",
497 "mediatek,mt2701-thermal";
501 clock-names = "therm", "auxadc";
503 reset-names = "therm";
506 nvmem-cells = <&thermal_calibration_data>;
507 nvmem-cell-names = "calibration-data";
511 compatible = "mediatek,mt7623-btif",
512 "mediatek,mtk-btif";
516 clock-names = "main";
517 reg-shift = <2>;
518 reg-io-width = <4>;
523 compatible = "mediatek,mt7623-nfc",
524 "mediatek,mt2701-nfc";
527 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
530 clock-names = "nfi_clk", "pad_clk";
532 ecc-engine = <&bch>;
533 #address-cells = <1>;
534 #size-cells = <0>;
538 compatible = "mediatek,mt7623-ecc",
539 "mediatek,mt2701-ecc";
543 clock-names = "nfiecc_clk";
548 compatible = "mediatek,mt7623-nor",
549 "mediatek,mt8173-nor";
553 clock-names = "spi", "sf";
554 #address-cells = <1>;
555 #size-cells = <0>;
560 compatible = "mediatek,mt7623-spi",
561 "mediatek,mt2701-spi";
562 #address-cells = <1>;
563 #size-cells = <0>;
569 clock-names = "parent-clk", "sel-clk", "spi-clk";
574 compatible = "mediatek,mt7623-spi",
575 "mediatek,mt2701-spi";
576 #address-cells = <1>;
577 #size-cells = <0>;
583 clock-names = "parent-clk", "sel-clk", "spi-clk";
588 compatible = "mediatek,mt7623-musb",
589 "mediatek,mtk-musb";
592 interrupt-names = "mc";
598 clock-names = "main","mcu","univpll";
599 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
603 u2phy1: t-phy@11210000 {
604 compatible = "mediatek,mt7623-tphy",
605 "mediatek,generic-tphy-v1";
607 #address-cells = <2>;
608 #size-cells = <2>;
612 u2port2: usb-phy@11210800 {
615 clock-names = "ref";
616 #phy-cells = <1>;
620 audsys: clock-controller@11220000 {
621 compatible = "mediatek,mt7623-audsys",
622 "mediatek,mt2701-audsys",
625 #clock-cells = <1>;
627 afe: audio-controller {
628 compatible = "mediatek,mt7623-audio",
629 "mediatek,mt2701-audio";
632 interrupt-names = "afe", "asys";
633 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
670 clock-names = "infra_sys_audio_clk",
705 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
709 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
711 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
716 compatible = "mediatek,mt7623-mmc",
717 "mediatek,mt2701-mmc";
722 clock-names = "source", "hclk";
727 compatible = "mediatek,mt7623-mmc",
728 "mediatek,mt2701-mmc";
733 clock-names = "source", "hclk";
738 compatible = "mediatek,mt7623-vdecsys",
739 "mediatek,mt2701-vdecsys",
742 #clock-cells = <1>;
746 compatible = "mediatek,mt7623-hifsys",
747 "mediatek,mt2701-hifsys",
750 #clock-cells = <1>;
751 #reset-cells = <1>;
755 compatible = "mediatek,mt7623-pcie";
761 reg-names = "subsys", "port0", "port1", "port2";
762 #address-cells = <3>;
763 #size-cells = <2>;
764 #interrupt-cells = <1>;
765 interrupt-map-mask = <0xf800 0 0 0>;
766 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
773 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
777 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
781 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
782 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
783 bus-range = <0x00 0xff>;
790 #address-cells = <3>;
791 #size-cells = <2>;
792 #interrupt-cells = <1>;
793 interrupt-map-mask = <0 0 0 0>;
794 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
801 #address-cells = <3>;
802 #size-cells = <2>;
803 #interrupt-cells = <1>;
804 interrupt-map-mask = <0 0 0 0>;
805 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
812 #address-cells = <3>;
813 #size-cells = <2>;
814 #interrupt-cells = <1>;
815 interrupt-map-mask = <0 0 0 0>;
816 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
822 pcie0_phy: t-phy@1a149000 {
823 compatible = "mediatek,mt7623-tphy",
824 "mediatek,generic-tphy-v1";
826 #address-cells = <2>;
827 #size-cells = <2>;
831 pcie0_port: pcie-phy@1a149900 {
834 clock-names = "ref";
835 #phy-cells = <1>;
840 pcie1_phy: t-phy@1a14a000 {
841 compatible = "mediatek,mt7623-tphy",
842 "mediatek,generic-tphy-v1";
844 #address-cells = <2>;
845 #size-cells = <2>;
849 pcie1_port: pcie-phy@1a14a900 {
852 clock-names = "ref";
853 #phy-cells = <1>;
859 compatible = "mediatek,mt7623-xhci",
860 "mediatek,mtk-xhci";
863 reg-names = "mac", "ippc";
867 clock-names = "sys_ck", "ref_ck";
868 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
873 u3phy1: t-phy@1a1c4000 {
874 compatible = "mediatek,mt7623-tphy",
875 "mediatek,generic-tphy-v1";
877 #address-cells = <2>;
878 #size-cells = <2>;
882 u2port0: usb-phy@1a1c4800 {
885 clock-names = "ref";
886 #phy-cells = <1>;
890 u3port0: usb-phy@1a1c4900 {
893 clock-names = "ref";
894 #phy-cells = <1>;
900 compatible = "mediatek,mt7623-xhci",
901 "mediatek,mtk-xhci";
904 reg-names = "mac", "ippc";
908 clock-names = "sys_ck", "ref_ck";
909 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
914 u3phy2: t-phy@1a244000 {
915 compatible = "mediatek,mt7623-tphy",
916 "mediatek,generic-tphy-v1";
918 #address-cells = <2>;
919 #size-cells = <2>;
923 u2port1: usb-phy@1a244800 {
926 clock-names = "ref";
927 #phy-cells = <1>;
931 u3port1: usb-phy@1a244900 {
934 clock-names = "ref";
935 #phy-cells = <1>;
941 compatible = "mediatek,mt7623-ethsys",
942 "mediatek,mt2701-ethsys",
945 #clock-cells = <1>;
946 #reset-cells = <1>;
949 hsdma: dma-controller@1b007000 {
950 compatible = "mediatek,mt7623-hsdma";
954 clock-names = "hsdma";
955 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
956 #dma-cells = <1>;
960 compatible = "mediatek,mt7623-eth",
961 "mediatek,mt2701-eth",
972 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
976 reset-names = "fe", "gmac", "ppe";
977 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
980 #address-cells = <1>;
981 #size-cells = <0>;
985 compatible = "mediatek,eth-mac";
991 compatible = "mediatek,eth-mac";
998 compatible = "mediatek,eip97-crypto";
1006 clock-names = "cryp";
1007 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1012 compatible = "mediatek,mt7623-bdpsys",
1013 "mediatek,mt2701-bdpsys",
1016 #clock-cells = <1>;
1021 cir_pins_a:cir-default {
1022 pins-cir {
1024 bias-disable;
1028 i2c0_pins_a: i2c0-default {
1029 pins-i2c0 {
1032 bias-disable;
1036 i2c1_pins_a: i2c1-default {
1037 pin-i2c1 {
1040 bias-disable;
1044 i2c1_pins_b: i2c1-alt {
1045 pin-i2c1 {
1048 bias-disable;
1052 i2c2_pins_a: i2c2-default {
1053 pin-i2c2 {
1056 bias-disable;
1060 i2c2_pins_b: i2c2-alt {
1061 pin-i2c2 {
1064 bias-disable;
1068 i2s0_pins_a: i2s0-default {
1069 pin-i2s0 {
1075 drive-strength = <MTK_DRIVE_12mA>;
1076 bias-pull-down;
1080 i2s1_pins_a: i2s1-default {
1081 pin-i2s1 {
1087 drive-strength = <MTK_DRIVE_12mA>;
1088 bias-pull-down;
1092 key_pins_a: keys-alt {
1093 pins-keys {
1096 input-enable;
1100 led_pins_a: leds-alt {
1101 pins-leds {
1109 pins-cmd-dat {
1119 input-enable;
1120 bias-pull-up;
1123 pins-clk {
1125 bias-pull-down;
1128 pins-rst {
1130 bias-pull-up;
1135 pins-cmd-dat {
1145 input-enable;
1146 drive-strength = <MTK_DRIVE_2mA>;
1147 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1150 pins-clk {
1152 drive-strength = <MTK_DRIVE_2mA>;
1153 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1156 pins-rst {
1158 bias-pull-up;
1163 pins-cmd-dat {
1169 input-enable;
1170 drive-strength = <MTK_DRIVE_4mA>;
1171 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1174 pins-clk {
1176 bias-pull-down;
1177 drive-strength = <MTK_DRIVE_4mA>;
1180 pins-wp {
1182 input-enable;
1183 bias-pull-up;
1186 pins-insert {
1188 bias-pull-up;
1193 pins-cmd-dat {
1199 input-enable;
1200 drive-strength = <MTK_DRIVE_4mA>;
1201 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1204 pins-clk {
1206 drive-strength = <MTK_DRIVE_4mA>;
1207 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1212 pins-ale {
1214 drive-strength = <MTK_DRIVE_8mA>;
1215 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1218 pins-dat {
1228 input-enable;
1229 drive-strength = <MTK_DRIVE_8mA>;
1230 bias-pull-up;
1233 pins-we {
1235 drive-strength = <MTK_DRIVE_8mA>;
1236 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1244 bias-disable;
1248 pwm_pins_a: pwm-default {
1249 pins-pwm {
1258 spi0_pins_a: spi0-default {
1259 pins-spi {
1264 bias-disable;
1268 spi1_pins_a: spi1-default {
1269 pins-spi {
1277 spi2_pins_a: spi2-default {
1278 pins-spi {
1286 uart0_pins_a: uart0-default {
1287 pins-dat {
1293 uart1_pins_a: uart1-default {
1294 pins-dat {
1300 uart2_pins_a: uart2-default {
1301 pins-dat {
1307 uart2_pins_b: uart2-alt {
1308 pins-dat {