Lines Matching +full:0 +full:xd4014000
16 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
45 reg = <0xd4200000 0x00200000>;
52 reg = <0xd4282000 0x1000>,
53 <0xd4284000 0x100>;
62 reg = <0x150 0x4>, <0x168 0x4>;
72 reg = <0x154 0x4>, <0x16c 0x4>;
82 reg = <0x1bc 0x4>, <0x1a4 0x4>;
92 reg = <0x1c0 0x4>, <0x1a8 0x4>;
102 reg = <0x158 0x4>, <0x170 0x4>;
112 reg = <0x1c4 0x4>, <0x1ac 0x4>;
122 reg = <0x1c8 0x4>, <0x1b0 0x4>;
132 reg = <0x15c 0x4>, <0x174 0x4>;
142 reg = <0x1cc 0x4>, <0x1b4 0x4>;
152 reg = <0x160 0x4>, <0x178 0x4>;
162 reg = <0x184 0x4>, <0x17c 0x4>;
172 reg = <0x188 0x4>, <0x180 0x4>;
182 reg = <0x1d0 0x4>, <0x1b8 0x4>;
189 reg = <0xd4207000 0x40>;
190 #phy-cells = <0>;
196 reg = <0xd4208000 0x200>;
207 reg = <0xf0001800 0x40>;
208 #phy-cells = <0>;
214 reg = <0xf0001000 0x200>;
221 #address-cells = <0x01>;
222 #size-cells = <0x00>;
228 reg = <0xf0002800 0x40>;
229 #phy-cells = <0>;
235 reg = <0xf0002000 0x200>;
242 #address-cells = <0x01>;
243 #size-cells = <0x00>;
249 reg = <0xd4280000 0x120>;
258 reg = <0xd4280800 0x120>;
267 reg = <0xd4281000 0x120>;
276 reg = <0xd4281800 0x120>;
285 reg = <0xd4217000 0x120>;
289 interrupts = <0>;
295 reg = <0xd420a000 0x800>;
301 #clock-cells = <0>;
308 reg = <0xd420a800 0x800>;
314 #clock-cells = <0>;
321 reg = <0xd420d000 0x2000>;
323 interrupts = <0>;
333 reg = <0xd420f000 0x2000>;
348 reg = <0xd4000000 0x00200000>;
353 reg = <0xd4014000 0x100>;
360 reg = <0xd4030000 0x1000>;
370 reg = <0xd4017000 0x1000>;
380 reg = <0xd4018000 0x1000>;
390 reg = <0xd4016000 0x1000>;
402 reg = <0xd4019000 0x1000>;
414 reg = <0xd4019000 0x4>;
418 reg = <0xd4019004 0x4>;
422 reg = <0xd4019008 0x4>;
426 reg = <0xd4019100 0x4>;
430 reg = <0xd4019104 0x4>;
434 reg = <0xd4019108 0x4>;
440 reg = <0xd4011000 0x70>;
445 #size-cells = <0>;
452 reg = <0xd4031000 0x70>;
454 interrupts = <0>;
458 #size-cells = <0>;
464 reg = <0xd4032000 0x70>;
470 #size-cells = <0>;
476 reg = <0xd4033000 0x70>;
482 #size-cells = <0>;
489 reg = <0xd4033800 0x70>;
495 #size-cells = <0>;
501 reg = <0xd4034000 0x70>;
507 #size-cells = <0>;
513 reg = <0xd4010000 0x1000>;
514 interrupts = <1>, <0>;
524 reg = <0xd4035000 0x1000>;
526 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
528 #size-cells = <0>;
534 reg = <0xd4036000 0x1000>;
538 #size-cells = <0>;
544 reg = <0xd4037000 0x1000>;
548 #size-cells = <0>;
554 reg = <0xd4039000 0x1000>;
558 #size-cells = <0>;
565 reg = <0xd0020000 0x1000>;
572 reg = <0xd4050000 0x2000>,
573 <0xd4282800 0x400>,
574 <0xd4015000 0x1000>;
583 reg = <0xe0000000 0x100>;
590 reg = <0xe0001000 0x1000>,
591 <0xe0000100 0x100>;
598 reg = <0xe0000600 0x20>;
603 reg = <0xe0000620 0x20>;