Lines Matching +full:global +full:- +full:regs
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
32 l2: l2-cache {
33 compatible = "marvell,tauros2-cache";
34 marvell,tauros2-cache-features = <0>;
37 gpu-subsystem {
38 compatible = "marvell,dove-gpu-subsystem";
43 i2c-mux {
44 compatible = "i2c-mux-pinctrl";
45 #address-cells = <1>;
46 #size-cells = <0>;
48 i2c-parent = <&i2c>;
50 pinctrl-names = "i2c0", "i2c1", "i2c2";
51 pinctrl-0 = <&pmx_i2cmux_0>;
52 pinctrl-1 = <&pmx_i2cmux_1>;
53 pinctrl-2 = <&pmx_i2cmux_2>;
57 #address-cells = <1>;
58 #size-cells = <0>;
64 #address-cells = <1>;
65 #size-cells = <0>;
72 #address-cells = <1>;
73 #size-cells = <0>;
80 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
81 #address-cells = <2>;
82 #size-cells = <1>;
84 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
85 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
87 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
88 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
94 compatible = "marvell,dove-pcie";
97 #address-cells = <3>;
98 #size-cells = <2>;
100 msi-parent = <&intc>;
101 bus-range = <0x00 0xff>;
113 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
116 marvell,pcie-port = <0>;
118 #address-cells = <3>;
119 #size-cells = <2>;
122 bus-range = <0x00 0xff>;
124 #interrupt-cells = <1>;
125 interrupt-names = "intx", "error";
127 interrupt-map-mask = <0 0 0 7>;
128 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
133 pcie0_intc: interrupt-controller {
134 interrupt-controller;
135 #interrupt-cells = <1>;
142 assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
145 marvell,pcie-port = <1>;
147 #address-cells = <3>;
148 #size-cells = <2>;
151 bus-range = <0x00 0xff>;
153 #interrupt-cells = <1>;
154 interrupt-names = "intx", "error";
156 interrupt-map-mask = <0 0 0 7>;
157 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
162 pcie1_intc: interrupt-controller {
163 interrupt-controller;
164 #interrupt-cells = <1>;
169 internal-regs {
170 compatible = "simple-bus";
171 #address-cells = <1>;
172 #size-cells = <1>;
173 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
174 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
179 compatible = "marvell,orion-spi";
180 #address-cells = <1>;
181 #size-cells = <0>;
182 cell-index = <0>;
186 pinctrl-0 = <&pmx_spi0>;
187 pinctrl-names = "default";
192 compatible = "marvell,mv64xxx-i2c";
194 #address-cells = <1>;
195 #size-cells = <0>;
197 clock-frequency = <400000>;
205 reg-shift = <2>;
214 reg-shift = <2>;
217 pinctrl-0 = <&pmx_uart1>;
218 pinctrl-names = "default";
225 reg-shift = <2>;
234 reg-shift = <2>;
241 compatible = "marvell,orion-spi";
242 #address-cells = <1>;
243 #size-cells = <0>;
244 cell-index = <1>;
251 mbusc: mbus-ctrl@20000 {
252 compatible = "marvell,mbus-controller";
256 sysc: system-ctrl@20000 {
257 compatible = "marvell,orion-system-controller";
261 bridge_intc: bridge-interrupt-ctrl@20110 {
262 compatible = "marvell,orion-bridge-intc";
263 interrupt-controller;
264 #interrupt-cells = <1>;
270 intc: interrupt-controller@20200 {
271 compatible = "marvell,orion-intc";
272 interrupt-controller;
273 #interrupt-cells = <1>;
278 compatible = "marvell,orion-timer";
280 interrupt-parent = <&bridge_intc>;
286 compatible = "marvell,orion-wdt";
288 interrupt-parent = <&bridge_intc>;
293 crypto: crypto-engine@30000 {
294 compatible = "marvell,dove-crypto";
296 reg-names = "regs";
299 marvell,crypto-srams = <&crypto_sram>;
300 marvell,crypto-sram-size = <0x800>;
304 ehci0: usb-host@50000 {
305 compatible = "marvell,orion-ehci";
312 ehci1: usb-host@51000 {
313 compatible = "marvell,orion-ehci";
320 xor0: dma-engine@60800 {
321 compatible = "marvell,orion-xor";
340 xor1: dma-engine@60900 {
341 compatible = "marvell,orion-xor";
360 sdio1: sdio-host@90000 {
361 compatible = "marvell,dove-sdhci";
365 pinctrl-0 = <&pmx_sdio1>;
366 pinctrl-names = "default";
370 eth: ethernet-ctrl@72000 {
371 compatible = "marvell,orion-eth";
372 #address-cells = <1>;
373 #size-cells = <0>;
376 marvell,tx-checksum-limit = <1600>;
379 ethernet-port@0 {
380 compatible = "marvell,orion-eth-port";
384 local-mac-address = [00 00 00 00 00 00];
388 mdio: mdio-bus@72004 {
389 compatible = "marvell,orion-mdio";
390 #address-cells = <1>;
391 #size-cells = <0>;
398 sdio0: sdio-host@92000 {
399 compatible = "marvell,dove-sdhci";
403 pinctrl-0 = <&pmx_sdio0>;
404 pinctrl-names = "default";
408 sata0: sata-host@a0000 {
409 compatible = "marvell,orion-sata";
414 phy-names = "port0";
415 nr-ports = <1>;
419 sata_phy0: sata-phy@a2000 {
420 compatible = "marvell,mvebu-sata-phy";
423 clock-names = "sata";
424 #phy-cells = <0>;
428 audio0: audio-controller@b0000 {
429 compatible = "marvell,dove-audio";
433 clock-names = "internal";
437 audio1: audio-controller@b4000 {
438 compatible = "marvell,dove-audio";
442 clock-names = "internal";
446 pmu: power-management@d0000 {
447 compatible = "marvell,dove-pmu", "simple-bus";
452 interrupt-controller;
453 #address-cells = <1>;
454 #size-cells = <1>;
455 #interrupt-cells = <1>;
456 #reset-cells = <1>;
459 vpu_domain: vpu-domain {
460 #power-domain-cells = <0>;
466 gpu_domain: gpu-domain {
467 #power-domain-cells = <0>;
474 thermal: thermal-diode@1c {
475 compatible = "marvell,dove-thermal";
479 gate_clk: clock-gating-ctrl@38 {
480 compatible = "marvell,dove-gating-clock";
483 #clock-cells = <1>;
486 divider_clk: core-clock@64 {
487 compatible = "marvell,dove-divider-clock";
489 #clock-cells = <1>;
492 pinctrl: pin-ctrl@200 {
493 compatible = "marvell,dove-pinctrl";
498 pmx_gpio_0: pmx-gpio-0 {
503 pmx_gpio_1: pmx-gpio-1 {
508 pmx_gpio_2: pmx-gpio-2 {
513 pmx_gpio_3: pmx-gpio-3 {
518 pmx_gpio_4: pmx-gpio-4 {
523 pmx_gpio_5: pmx-gpio-5 {
528 pmx_gpio_6: pmx-gpio-6 {
533 pmx_gpio_7: pmx-gpio-7 {
538 pmx_gpio_8: pmx-gpio-8 {
543 pmx_gpio_9: pmx-gpio-9 {
548 pmx_pcie1_clkreq: pmx-pcie1-clkreq {
553 pmx_gpio_10: pmx-gpio-10 {
558 pmx_gpio_11: pmx-gpio-11 {
563 pmx_pcie0_clkreq: pmx-pcie0-clkreq {
568 pmx_gpio_12: pmx-gpio-12 {
573 pmx_gpio_13: pmx-gpio-13 {
578 pmx_audio1_extclk: pmx-audio1-extclk {
583 pmx_gpio_14: pmx-gpio-14 {
588 pmx_gpio_15: pmx-gpio-15 {
593 pmx_gpio_16: pmx-gpio-16 {
598 pmx_gpio_17: pmx-gpio-17 {
603 pmx_gpio_18: pmx-gpio-18 {
608 pmx_gpio_19: pmx-gpio-19 {
613 pmx_gpio_20: pmx-gpio-20 {
618 pmx_gpio_21: pmx-gpio-21 {
623 pmx_camera: pmx-camera {
628 pmx_camera_gpio: pmx-camera-gpio {
633 pmx_sdio0: pmx-sdio0 {
638 pmx_sdio0_gpio: pmx-sdio0-gpio {
643 pmx_sdio1: pmx-sdio1 {
648 pmx_sdio1_gpio: pmx-sdio1-gpio {
653 pmx_audio1_gpio: pmx-audio1-gpio {
658 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
663 pmx_spi0: pmx-spi0 {
668 pmx_spi0_gpio: pmx-spi0-gpio {
673 pmx_spi1_4_7: pmx-spi1-4-7 {
679 pmx_spi1_20_23: pmx-spi1-20-23 {
685 pmx_uart1: pmx-uart1 {
690 pmx_uart1_gpio: pmx-uart1-gpio {
695 pmx_nand: pmx-nand {
700 pmx_nand_gpo: pmx-nand-gpo {
705 pmx_i2c1: pmx-i2c1 {
710 pmx_i2c2: pmx-i2c2 {
715 pmx_ssp_i2c2: pmx-ssp-i2c2 {
720 pmx_i2cmux_0: pmx-i2cmux-0 {
722 marvell,function = "twsi-opt1";
725 pmx_i2cmux_1: pmx-i2cmux-1 {
727 marvell,function = "twsi-opt2";
730 pmx_i2cmux_2: pmx-i2cmux-2 {
732 marvell,function = "twsi-opt3";
736 core_clk: core-clocks@214 {
737 compatible = "marvell,dove-core-clock";
739 #clock-cells = <1>;
742 gpio0: gpio-ctrl@400 {
743 compatible = "marvell,orion-gpio";
744 #gpio-cells = <2>;
745 gpio-controller;
748 interrupt-controller;
749 #interrupt-cells = <2>;
750 interrupt-parent = <&intc>;
754 gpio1: gpio-ctrl@420 {
755 compatible = "marvell,orion-gpio";
756 #gpio-cells = <2>;
757 gpio-controller;
760 interrupt-controller;
761 #interrupt-cells = <2>;
762 interrupt-parent = <&intc>;
766 rtc: real-time-clock@8500 {
767 compatible = "marvell,orion-rtc";
773 gconf: global-config@e802c {
774 compatible = "marvell,dove-global-config",
779 gpio2: gpio-ctrl@e8400 {
780 compatible = "marvell,orion-gpio";
781 #gpio-cells = <2>;
782 gpio-controller;
787 lcd1: lcd-controller@810000 {
788 compatible = "marvell,dove-lcd";
794 lcd0: lcd-controller@820000 {
795 compatible = "marvell,dove-lcd";
802 compatible = "mmio-sram";
805 #address-cells = <1>;
806 #size-cells = <1>;
811 clock-names = "core";
814 power-domains = <&gpu_domain>;