Lines Matching +full:sata3 +full:- +full:ahci
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
38 #address-cells = <2>;
39 #size-cells = <1>;
41 interrupt-parent = <&gic>;
42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
54 #address-cells = <1>;
55 #size-cells = <1>;
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
64 #address-cells = <1>;
65 #size-cells = <1>;
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
74 #address-cells = <1>;
75 #size-cells = <1>;
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
84 #address-cells = <1>;
85 #size-cells = <1>;
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
94 #address-cells = <1>;
95 #size-cells = <1>;
100 internal-regs {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
107 compatible = "marvell,armada-xp-sdram-controller";
111 L2: cache-controller@8000 {
112 compatible = "arm,pl310-cache";
114 cache-unified;
115 cache-level = <2>;
116 arm,double-linefill-incr = <0>;
117 arm,double-linefill-wrap = <0>;
118 arm,double-linefill = <0>;
119 prefetch-data = <1>;
123 compatible = "arm,cortex-a9-scu";
128 compatible = "arm,cortex-a9-global-timer";
135 compatible = "arm,cortex-a9-twd-timer";
141 gic: interrupt-controller@d000 {
142 compatible = "arm,cortex-a9-gic";
143 #interrupt-cells = <3>;
144 #size-cells = <0>;
145 interrupt-controller;
151 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
153 #address-cells = <1>;
154 #size-cells = <0>;
161 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
163 #address-cells = <1>;
164 #size-cells = <0>;
171 compatible = "marvell,armada-38x-uart", "ns16550a";
173 reg-shift = <2>;
175 reg-io-width = <1>;
181 compatible = "marvell,armada-38x-uart", "ns16550a";
183 reg-shift = <2>;
185 reg-io-width = <1>;
193 ge0_rgmii_pins: ge-rgmii-pins-0 {
201 ge1_rgmii_pins: ge-rgmii-pins-1 {
209 i2c0_pins: i2c-pins-0 {
214 mdio_pins: mdio-pins {
219 ref_clk0_pins: ref-clk-pins-0 {
224 ref_clk1_pins: ref-clk-pins-1 {
229 spi0_pins: spi-pins-0 {
235 spi1_pins: spi-pins-1 {
241 nand_pins: nand-pins {
250 nand_rb: nand-rb {
255 uart0_pins: uart-pins-0 {
260 uart1_pins: uart-pins-1 {
265 sdhci_pins: sdhci-pins {
273 sata0_pins: sata-pins-0 {
278 sata1_pins: sata-pins-1 {
283 sata2_pins: sata-pins-2 {
288 sata3_pins: sata-pins-3 {
290 marvell,function = "sata3";
293 i2s_pins: i2s-pins {
300 spdif_pins: spdif-pins {
307 compatible = "marvell,armada-370-gpio",
308 "marvell,orion-gpio";
310 reg-names = "gpio", "pwm";
312 gpio-controller;
313 gpio-ranges = <&pinctrl 0 0 32>;
314 #gpio-cells = <2>;
315 #pwm-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
326 compatible = "marvell,armada-370-gpio",
327 "marvell,orion-gpio";
329 reg-names = "gpio", "pwm";
331 gpio-controller;
332 gpio-ranges = <&pinctrl 0 32 28>;
333 #gpio-cells = <2>;
334 #pwm-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
344 systemc: system-controller@18200 {
345 compatible = "marvell,armada-380-system-controller",
346 "marvell,armada-370-xp-system-controller";
350 gateclk: clock-gating-control@18220 {
351 compatible = "marvell,armada-380-gating-clock";
354 #clock-cells = <1>;
358 compatible = "marvell,armada-380-comphy";
359 reg-names = "comphy", "conf";
361 #address-cells = <1>;
362 #size-cells = <0>;
366 #phy-cells = <1>;
371 #phy-cells = <1>;
376 #phy-cells = <1>;
381 #phy-cells = <1>;
386 #phy-cells = <1>;
391 #phy-cells = <1>;
395 coreclk: mvebu-sar@18600 {
396 compatible = "marvell,armada-380-core-clock";
398 #clock-cells = <1>;
401 mbusc: mbus-controller@20000 {
402 compatible = "marvell,mbus-controller";
407 mpic: interrupt-controller@20a00 {
410 #interrupt-cells = <1>;
411 #size-cells = <1>;
412 interrupt-controller;
413 msi-controller;
418 compatible = "marvell,armada-380-timer",
419 "marvell,armada-xp-timer";
421 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
428 clock-names = "nbclk", "fixed";
432 compatible = "marvell,armada-380-wdt";
435 clock-names = "nbclk", "fixed";
436 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
441 compatible = "marvell,armada-370-cpu-reset";
445 mpcore-soc-ctrl@20d20 {
446 compatible = "marvell,armada-380-mpcore-soc-ctrl";
450 coherencyfab: coherency-fabric@21010 {
451 compatible = "marvell,armada-380-coherency-fabric";
456 compatible = "marvell,armada-380-pmsu";
468 * from the one used in U-Boot and the
473 compatible = "marvell,armada-370-neta";
475 interrupts-extended = <&mpic 8>;
477 tx-csum-limit = <9800>;
482 compatible = "marvell,armada-370-neta";
484 interrupts-extended = <&mpic 10>;
490 compatible = "marvell,armada-370-neta";
492 interrupts-extended = <&mpic 12>;
498 compatible = "marvell,orion-ehci";
506 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
526 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "marvell,orion-mdio";
554 compatible = "marvell,armada-38x-crypto";
556 reg-names = "regs";
561 clock-names = "cesa0", "cesa1",
563 marvell,crypto-srams = <&crypto_sram0>,
565 marvell,crypto-sram-size = <0x800>;
569 compatible = "marvell,armada-380-rtc";
571 reg-names = "rtc", "rtc-soc";
576 compatible = "marvell,armada-380-ahci";
584 compatible = "marvell,armada-380-neta-bm";
587 internal-mem = <&bm_bppi>;
592 compatible = "marvell,armada-380-ahci";
600 compatible = "marvell,armada-380-corediv-clock";
602 #clock-cells = <1>;
604 clock-output-names = "nand";
608 compatible = "marvell,armada380-thermal";
613 nand_controller: nand-controller@d0000 {
614 compatible = "marvell,armada370-nand-controller";
616 #address-cells = <1>;
617 #size-cells = <0>;
624 compatible = "marvell,armada-380-sdhci";
625 reg-names = "sdhci", "mbus", "conf-sdio3";
631 mrvl,clk-delay-cycles = <0x1F>;
635 audio_controller: audio-controller@e8000 {
636 #sound-dai-cells = <1>;
637 compatible = "marvell,armada-380-audio";
640 reg-names = "i2s_regs", "pll_regs", "soc_ctrl";
643 clock-names = "internal";
648 compatible = "marvell,armada-380-xhci";
656 compatible = "marvell,armada-380-xhci";
664 crypto_sram0: sa-sram0 {
665 compatible = "mmio-sram";
668 #address-cells = <1>;
669 #size-cells = <1>;
673 crypto_sram1: sa-sram1 {
674 compatible = "mmio-sram";
677 #address-cells = <1>;
678 #size-cells = <1>;
682 bm_bppi: bm-bppi {
683 compatible = "mmio-sram";
686 #address-cells = <1>;
687 #size-cells = <1>;
689 no-memory-wc;
694 compatible = "marvell,armada-380-spi",
695 "marvell,orion-spi";
697 #address-cells = <1>;
698 #size-cells = <0>;
699 cell-index = <0>;
706 compatible = "marvell,armada-380-spi",
707 "marvell,orion-spi";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 cell-index = <1>;
721 compatible = "fixed-clock";
722 #clock-cells = <0>;
723 clock-frequency = <1000000000>;
728 compatible = "fixed-clock";
729 #clock-cells = <0>;
730 clock-frequency = <25000000>;