Lines Matching +full:0 +full:xfff00000
30 reg = <0x00000000 0x80000000>; /* 2GB */
34 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
35 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
41 pinctrl-0 = <&i2c0_pins>;
52 pinctrl-0 = <&uart0_pins>;
60 * The Reference Clock 0 is used to provide a
63 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
83 pinctrl-0 = <&mdio_pins>;
89 phy1: ethernet-phy@0 {
90 reg = <0>;
97 nand@0 {
98 reg = <0>;
99 label = "pxa3xx_nand-0";
100 nand-rb = <0>;
107 partition@0 {
108 reg = <0x00000000 0x40000000>;
120 /* Port 0, Lane 0 */
126 pinctrl-0 = <&spi1_pins>;
129 flash@0 {
133 reg = <0>; /* Chip select 0 */
141 partition@0 {
142 reg = <0x00000000 0x00100000>;
146 reg = <0x00100000 0x00040000>;