Lines Matching +full:cpu +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
32 cpu = <&CPU0>;
35 cpu = <&CPU1>;
38 cpu = <&CPU2>;
41 cpu = <&CPU3>;
46 cpu = <&CPU4>;
49 cpu = <&CPU5>;
52 cpu = <&CPU6>;
55 cpu = <&CPU7>;
60 cpu = <&CPU8>;
63 cpu = <&CPU9>;
66 cpu = <&CPU10>;
69 cpu = <&CPU11>;
74 cpu = <&CPU12>;
77 cpu = <&CPU13>;
80 cpu = <&CPU14>;
83 cpu = <&CPU15>;
87 CPU0: cpu@0 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a15";
92 CPU1: cpu@1 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a15";
95 reg = <1>;
97 CPU2: cpu@2 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a15";
102 CPU3: cpu@3 {
103 device_type = "cpu";
104 compatible = "arm,cortex-a15";
107 CPU4: cpu@100 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a15";
112 CPU5: cpu@101 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a15";
117 CPU6: cpu@102 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a15";
122 CPU7: cpu@103 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a15";
127 CPU8: cpu@200 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a15";
132 CPU9: cpu@201 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a15";
137 CPU10: cpu@202 {
138 device_type = "cpu";
139 compatible = "arm,cortex-a15";
142 CPU11: cpu@203 {
143 device_type = "cpu";
144 compatible = "arm,cortex-a15";
147 CPU12: cpu@300 {
148 device_type = "cpu";
149 compatible = "arm,cortex-a15";
152 CPU13: cpu@301 {
153 device_type = "cpu";
154 compatible = "arm,cortex-a15";
157 CPU14: cpu@302 {
158 device_type = "cpu";
159 compatible = "arm,cortex-a15";
162 CPU15: cpu@303 {
163 device_type = "cpu";
164 compatible = "arm,cortex-a15";
170 compatible = "arm,armv7-timer";
171 interrupt-parent = <&gic>;
172 interrupts = <1 13 0xf08>,
173 <1 14 0xf08>,
174 <1 11 0xf08>,
175 <1 10 0xf08>;
179 #clock-cells = <0>;
180 compatible = "fixed-clock";
181 clock-frequency = <50000000>;
185 #clock-cells = <0>;
186 compatible = "fixed-clock";
187 clock-frequency = <168000000>;
191 #clock-cells = <0>;
192 compatible = "fixed-clock";
193 clock-frequency = <375000000>;
197 /* It's a 32-bit SoC. */
198 #address-cells = <1>;
199 #size-cells = <1>;
200 compatible = "simple-bus";
201 interrupt-parent = <&gic>;
204 gic: interrupt-controller@c01000 {
205 compatible = "hisilicon,hip04-intc";
206 #interrupt-cells = <3>;
207 #address-cells = <0>;
208 interrupt-controller;
209 interrupts = <1 9 0xf04>;
221 compatible = "hisilicon,hip04-fabric";
230 clock-names = "timer0clk", "timer1clk", "apb_pclk";
233 arm-pmu {
234 compatible = "arm,cortex-a15-pmu";
254 compatible = "snps,dw-apb-uart";
258 clock-names = "baudclk", "apb_pclk";
259 reg-shift = <2>;
264 compatible = "hisilicon,hisi-ahci";
272 compatible = "arm,coresight-etb10", "arm,primecell";
276 clock-names = "apb_pclk";
277 in-ports {
280 remote-endpoint = <&replicator0_out_port0>;
287 compatible = "arm,coresight-etb10", "arm,primecell";
291 clock-names = "apb_pclk";
292 in-ports {
295 remote-endpoint = <&replicator1_out_port0>;
302 compatible = "arm,coresight-etb10", "arm,primecell";
306 clock-names = "apb_pclk";
307 in-ports {
310 remote-endpoint = <&replicator2_out_port0>;
317 compatible = "arm,coresight-etb10", "arm,primecell";
321 clock-names = "apb_pclk";
322 in-ports {
325 remote-endpoint = <&replicator3_out_port0>;
332 compatible = "arm,coresight-tpiu", "arm,primecell";
336 clock-names = "apb_pclk";
337 in-ports {
340 remote-endpoint = <&funnel4_out_port0>;
347 /* non-configurable replicators don't show up on the
350 compatible = "arm,coresight-static-replicator";
352 out-ports {
353 #address-cells = <1>;
354 #size-cells = <0>;
360 remote-endpoint = <&etb0_in_port>;
364 port@1 {
365 reg = <1>;
367 remote-endpoint = <&funnel4_in_port0>;
372 in-ports {
375 remote-endpoint = <&funnel0_out_port0>;
382 /* non-configurable replicators don't show up on the
385 compatible = "arm,coresight-static-replicator";
387 out-ports {
388 #address-cells = <1>;
389 #size-cells = <0>;
395 remote-endpoint = <&etb1_in_port>;
399 port@1 {
400 reg = <1>;
402 remote-endpoint = <&funnel4_in_port1>;
407 in-ports {
410 remote-endpoint = <&funnel1_out_port0>;
417 /* non-configurable replicators don't show up on the
420 compatible = "arm,coresight-static-replicator";
422 out-ports {
423 #address-cells = <1>;
424 #size-cells = <0>;
429 remote-endpoint = <&etb2_in_port>;
433 port@1 {
434 reg = <1>;
436 remote-endpoint = <&funnel4_in_port2>;
441 in-ports {
444 remote-endpoint = <&funnel2_out_port0>;
451 /* non-configurable replicators don't show up on the
454 compatible = "arm,coresight-static-replicator";
456 out-ports {
457 #address-cells = <1>;
458 #size-cells = <0>;
463 remote-endpoint = <&etb3_in_port>;
467 port@1 {
468 reg = <1>;
470 remote-endpoint = <&funnel4_in_port3>;
475 in-ports {
478 remote-endpoint = <&funnel3_out_port0>;
485 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
489 clock-names = "apb_pclk";
490 out-ports {
493 remote-endpoint =
499 in-ports {
500 #address-cells = <1>;
501 #size-cells = <0>;
506 remote-endpoint = <&ptm0_out_port>;
510 port@1 {
511 reg = <1>;
513 remote-endpoint = <&ptm1_out_port>;
520 remote-endpoint = <&ptm2_out_port>;
527 remote-endpoint = <&ptm3_out_port>;
534 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
538 clock-names = "apb_pclk";
539 out-ports {
542 remote-endpoint =
548 in-ports {
549 #address-cells = <1>;
550 #size-cells = <0>;
555 remote-endpoint = <&ptm4_out_port>;
559 port@1 {
560 reg = <1>;
562 remote-endpoint = <&ptm5_out_port>;
569 remote-endpoint = <&ptm6_out_port>;
576 remote-endpoint = <&ptm7_out_port>;
583 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
587 clock-names = "apb_pclk";
588 out-ports {
591 remote-endpoint =
597 in-ports {
598 #address-cells = <1>;
599 #size-cells = <0>;
604 remote-endpoint = <&ptm8_out_port>;
608 port@1 {
609 reg = <1>;
611 remote-endpoint = <&ptm9_out_port>;
618 remote-endpoint = <&ptm10_out_port>;
625 remote-endpoint = <&ptm11_out_port>;
632 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
636 clock-names = "apb_pclk";
637 out-ports {
640 remote-endpoint =
646 in-ports {
647 #address-cells = <1>;
648 #size-cells = <0>;
653 remote-endpoint = <&ptm12_out_port>;
657 port@1 {
658 reg = <1>;
660 remote-endpoint = <&ptm13_out_port>;
667 remote-endpoint = <&ptm14_out_port>;
674 remote-endpoint = <&ptm15_out_port>;
681 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
685 clock-names = "apb_pclk";
686 out-ports {
689 remote-endpoint = <&tpiu_in_port>;
694 in-ports {
695 #address-cells = <1>;
696 #size-cells = <0>;
701 remote-endpoint =
706 port@1 {
707 reg = <1>;
709 remote-endpoint =
717 remote-endpoint =
725 remote-endpoint =
733 compatible = "arm,coresight-etm3x", "arm,primecell";
737 clock-names = "apb_pclk";
738 cpu = <&CPU0>;
739 out-ports {
742 remote-endpoint = <&funnel0_in_port0>;
749 compatible = "arm,coresight-etm3x", "arm,primecell";
753 clock-names = "apb_pclk";
754 cpu = <&CPU1>;
755 out-ports {
758 remote-endpoint = <&funnel0_in_port1>;
765 compatible = "arm,coresight-etm3x", "arm,primecell";
769 clock-names = "apb_pclk";
770 cpu = <&CPU2>;
771 out-ports {
774 remote-endpoint = <&funnel0_in_port2>;
781 compatible = "arm,coresight-etm3x", "arm,primecell";
785 clock-names = "apb_pclk";
786 cpu = <&CPU3>;
787 out-ports {
790 remote-endpoint = <&funnel0_in_port3>;
797 compatible = "arm,coresight-etm3x", "arm,primecell";
801 clock-names = "apb_pclk";
802 cpu = <&CPU4>;
803 out-ports {
806 remote-endpoint = <&funnel1_in_port0>;
813 compatible = "arm,coresight-etm3x", "arm,primecell";
817 clock-names = "apb_pclk";
818 cpu = <&CPU5>;
819 out-ports {
822 remote-endpoint = <&funnel1_in_port1>;
829 compatible = "arm,coresight-etm3x", "arm,primecell";
833 clock-names = "apb_pclk";
834 cpu = <&CPU6>;
835 out-ports {
838 remote-endpoint = <&funnel1_in_port2>;
845 compatible = "arm,coresight-etm3x", "arm,primecell";
849 clock-names = "apb_pclk";
850 cpu = <&CPU7>;
851 out-ports {
854 remote-endpoint = <&funnel1_in_port3>;
861 compatible = "arm,coresight-etm3x", "arm,primecell";
865 clock-names = "apb_pclk";
866 cpu = <&CPU8>;
867 out-ports {
870 remote-endpoint = <&funnel2_in_port0>;
877 compatible = "arm,coresight-etm3x", "arm,primecell";
880 clock-names = "apb_pclk";
881 cpu = <&CPU9>;
882 out-ports {
885 remote-endpoint = <&funnel2_in_port1>;
892 compatible = "arm,coresight-etm3x", "arm,primecell";
896 clock-names = "apb_pclk";
897 cpu = <&CPU10>;
898 out-ports {
901 remote-endpoint = <&funnel2_in_port2>;
908 compatible = "arm,coresight-etm3x", "arm,primecell";
912 clock-names = "apb_pclk";
913 cpu = <&CPU11>;
914 out-ports {
917 remote-endpoint = <&funnel2_in_port3>;
924 compatible = "arm,coresight-etm3x", "arm,primecell";
928 clock-names = "apb_pclk";
929 cpu = <&CPU12>;
930 out-ports {
933 remote-endpoint = <&funnel3_in_port0>;
940 compatible = "arm,coresight-etm3x", "arm,primecell";
944 clock-names = "apb_pclk";
945 cpu = <&CPU13>;
946 out-ports {
949 remote-endpoint = <&funnel3_in_port1>;
956 compatible = "arm,coresight-etm3x", "arm,primecell";
960 clock-names = "apb_pclk";
961 cpu = <&CPU14>;
962 out-ports {
965 remote-endpoint = <&funnel3_in_port2>;
972 compatible = "arm,coresight-etm3x", "arm,primecell";
976 clock-names = "apb_pclk";
977 cpu = <&CPU15>;
978 out-ports {
981 remote-endpoint = <&funnel3_in_port3>;