Lines Matching +full:0 +full:xa000000
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
27 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0>;
110 reg = <0x100>;
115 reg = <0x101>;
120 reg = <0x102>;
125 reg = <0x103>;
130 reg = <0x200>;
135 reg = <0x201>;
140 reg = <0x202>;
145 reg = <0x203>;
150 reg = <0x300>;
155 reg = <0x301>;
160 reg = <0x302>;
165 reg = <0x303>;
172 interrupts = <1 13 0xf08>,
173 <1 14 0xf08>,
174 <1 11 0xf08>,
175 <1 10 0xf08>;
179 #clock-cells = <0>;
185 #clock-cells = <0>;
191 #clock-cells = <0>;
202 ranges = <0 0 0xe0000000 0x10000000>;
207 #address-cells = <0>;
209 interrupts = <1 9 0xf04>;
211 reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
212 <0xc04000 0x2000>, <0xc06000 0x2000>;
217 reg = <0x3e00000 0x00100000>;
222 reg = <0x302a000 0x1000>;
227 reg = <0x3000000 0x1000>;
228 interrupts = <0 224 4>;
235 interrupts = <0 64 4>,
236 <0 65 4>,
237 <0 66 4>,
238 <0 67 4>,
239 <0 68 4>,
240 <0 69 4>,
241 <0 70 4>,
242 <0 71 4>,
243 <0 72 4>,
244 <0 73 4>,
245 <0 74 4>,
246 <0 75 4>,
247 <0 76 4>,
248 <0 77 4>,
249 <0 78 4>,
250 <0 79 4>;
255 reg = <0x4007000 0x1000>;
256 interrupts = <0 381 4>;
265 reg = <0xa000000 0x1000000>;
266 interrupts = <0 372 4>;
271 etb@0,e3c42000 {
273 reg = <0 0xe3c42000 0 0x1000>;
279 etb0_in_port: endpoint@0 {
286 etb@0,e3c82000 {
288 reg = <0 0xe3c82000 0 0x1000>;
294 etb1_in_port: endpoint@0 {
301 etb@0,e3cc2000 {
303 reg = <0 0xe3cc2000 0 0x1000>;
309 etb2_in_port: endpoint@0 {
316 etb@0,e3d02000 {
318 reg = <0 0xe3d02000 0 0x1000>;
324 etb3_in_port: endpoint@0 {
331 tpiu@0,e3c05000 {
333 reg = <0 0xe3c05000 0 0x1000>;
339 tpiu_in_port: endpoint@0 {
354 #size-cells = <0>;
357 port@0 {
358 reg = <0>;
389 #size-cells = <0>;
392 port@0 {
393 reg = <0>;
424 #size-cells = <0>;
426 port@0 {
427 reg = <0>;
458 #size-cells = <0>;
460 port@0 {
461 reg = <0>;
484 funnel@0,e3c41000 {
486 reg = <0 0xe3c41000 0 0x1000>;
501 #size-cells = <0>;
503 port@0 {
504 reg = <0>;
533 funnel@0,e3c81000 {
535 reg = <0 0xe3c81000 0 0x1000>;
550 #size-cells = <0>;
552 port@0 {
553 reg = <0>;
582 funnel@0,e3cc1000 {
584 reg = <0 0xe3cc1000 0 0x1000>;
599 #size-cells = <0>;
601 port@0 {
602 reg = <0>;
631 funnel@0,e3d01000 {
633 reg = <0 0xe3d01000 0 0x1000>;
648 #size-cells = <0>;
650 port@0 {
651 reg = <0>;
680 funnel@0,e3c04000 {
682 reg = <0 0xe3c04000 0 0x1000>;
696 #size-cells = <0>;
698 port@0 {
699 reg = <0>;
732 ptm@0,e3c7c000 {
734 reg = <0 0xe3c7c000 0 0x1000>;
748 ptm@0,e3c7d000 {
750 reg = <0 0xe3c7d000 0 0x1000>;
764 ptm@0,e3c7e000 {
766 reg = <0 0xe3c7e000 0 0x1000>;
780 ptm@0,e3c7f000 {
782 reg = <0 0xe3c7f000 0 0x1000>;
796 ptm@0,e3cbc000 {
798 reg = <0 0xe3cbc000 0 0x1000>;
812 ptm@0,e3cbd000 {
814 reg = <0 0xe3cbd000 0 0x1000>;
828 ptm@0,e3cbe000 {
830 reg = <0 0xe3cbe000 0 0x1000>;
844 ptm@0,e3cbf000 {
846 reg = <0 0xe3cbf000 0 0x1000>;
860 ptm@0,e3cfc000 {
862 reg = <0 0xe3cfc000 0 0x1000>;
876 ptm@0,e3cfd000 {
878 reg = <0 0xe3cfd000 0 0x1000>;
891 ptm@0,e3cfe000 {
893 reg = <0 0xe3cfe000 0 0x1000>;
907 ptm@0,e3cff000 {
909 reg = <0 0xe3cff000 0 0x1000>;
923 ptm@0,e3d3c000 {
925 reg = <0 0xe3d3c000 0 0x1000>;
939 ptm@0,e3d3d000 {
941 reg = <0 0xe3d3d000 0 0x1000>;
955 ptm@0,e3d3e000 {
957 reg = <0 0xe3d3e000 0 0x1000>;
971 ptm@0,e3d3f000 {
973 reg = <0 0xe3d3f000 0 0x1000>;