Lines Matching +full:hi3620 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-only
3 * HiSilicon Ltd. Hi3620 SoC
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
33 #address-cells = <1>;
34 #size-cells = <0>;
35 enable-method = "hisilicon,hi3620-smp";
39 compatible = "arm,cortex-a9";
41 next-level-cache = <&L2>;
45 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a9";
55 next-level-cache = <&L2>;
59 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
66 amba-bus {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
74 L2: cache-controller {
75 compatible = "arm,pl310-cache";
78 cache-unified;
79 cache-level = <2>;
82 gic: interrupt-controller@1000 {
83 compatible = "arm,cortex-a9-gic";
84 #interrupt-cells = <3>;
85 #address-cells = <0>;
86 interrupt-controller;
91 sysctrl: system-controller@802000 {
93 #address-cells = <1>;
94 #size-cells = <1>;
98 smp-offset = <0x31c>;
99 resume-offset = <0x308>;
100 reboot-offset = <0x4>;
102 clock: clock@0 { label
103 compatible = "hisilicon,hi3620-clock";
105 #clock-cells = <1>;
114 clocks = <&clock HI3620_TIMER0_MUX>,
115 <&clock HI3620_TIMER1_MUX>,
116 <&clock HI3620_TIMER0_MUX>;
117 clock-names = "timer0clk", "timer1clk", "apb_pclk";
126 clocks = <&clock HI3620_TIMER2_MUX>,
127 <&clock HI3620_TIMER3_MUX>,
128 <&clock HI3620_TIMER2_MUX>;
129 clock-names = "timer0clk", "timer1clk", "apb_pclk";
138 clocks = <&clock HI3620_TIMER4_MUX>,
139 <&clock HI3620_TIMER5_MUX>,
140 <&clock HI3620_TIMER4_MUX>;
141 clock-names = "timer0lck", "timer1clk", "apb_pclk";
150 clocks = <&clock HI3620_TIMER6_MUX>,
151 <&clock HI3620_TIMER7_MUX>,
152 <&clock HI3620_TIMER6_MUX>;
153 clock-names = "timer0clk", "timer1clk", "apb_pclk";
162 clocks = <&clock HI3620_TIMER8_MUX>,
163 <&clock HI3620_TIMER9_MUX>,
164 <&clock HI3620_TIMER8_MUX>;
165 clock-names = "timer0clk", "timer1clk", "apb_pclk";
170 compatible = "arm,cortex-a9-twd-timer";
179 clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>;
180 clock-names = "uartclk", "apb_pclk";
188 clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>;
189 clock-names = "uartclk", "apb_pclk";
197 clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>;
198 clock-names = "uartclk", "apb_pclk";
206 clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>;
207 clock-names = "uartclk", "apb_pclk";
215 clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>;
216 clock-names = "uartclk", "apb_pclk";
224 gpio-controller;
225 #gpio-cells = <2>;
226 gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 clocks = <&clock HI3620_GPIOCLK0>;
231 clock-names = "apb_pclk";
238 gpio-controller;
239 #gpio-cells = <2>;
240 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
243 interrupt-controller;
244 #interrupt-cells = <2>;
245 clocks = <&clock HI3620_GPIOCLK1>;
246 clock-names = "apb_pclk";
253 gpio-controller;
254 #gpio-cells = <2>;
255 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
258 interrupt-controller;
259 #interrupt-cells = <2>;
260 clocks = <&clock HI3620_GPIOCLK2>;
261 clock-names = "apb_pclk";
268 gpio-controller;
269 #gpio-cells = <2>;
270 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 clocks = <&clock HI3620_GPIOCLK3>;
276 clock-names = "apb_pclk";
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 clocks = <&clock HI3620_GPIOCLK4>;
291 clock-names = "apb_pclk";
298 gpio-controller;
299 #gpio-cells = <2>;
300 gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 clocks = <&clock HI3620_GPIOCLK5>;
306 clock-names = "apb_pclk";
313 gpio-controller;
314 #gpio-cells = <2>;
315 gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 clocks = <&clock HI3620_GPIOCLK6>;
321 clock-names = "apb_pclk";
328 gpio-controller;
329 #gpio-cells = <2>;
330 gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
333 interrupt-controller;
334 #interrupt-cells = <2>;
335 clocks = <&clock HI3620_GPIOCLK7>;
336 clock-names = "apb_pclk";
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 clocks = <&clock HI3620_GPIOCLK8>;
351 clock-names = "apb_pclk";
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
363 interrupt-controller;
364 #interrupt-cells = <2>;
365 clocks = <&clock HI3620_GPIOCLK9>;
366 clock-names = "apb_pclk";
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 clocks = <&clock HI3620_GPIOCLK10>;
380 clock-names = "apb_pclk";
387 gpio-controller;
388 #gpio-cells = <2>;
389 gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 clocks = <&clock HI3620_GPIOCLK11>;
395 clock-names = "apb_pclk";
402 gpio-controller;
403 #gpio-cells = <2>;
404 gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 clocks = <&clock HI3620_GPIOCLK12>;
410 clock-names = "apb_pclk";
417 gpio-controller;
418 #gpio-cells = <2>;
419 gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 clocks = <&clock HI3620_GPIOCLK13>;
425 clock-names = "apb_pclk";
432 gpio-controller;
433 #gpio-cells = <2>;
434 gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 clocks = <&clock HI3620_GPIOCLK14>;
440 clock-names = "apb_pclk";
447 gpio-controller;
448 #gpio-cells = <2>;
449 gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 clocks = <&clock HI3620_GPIOCLK15>;
455 clock-names = "apb_pclk";
462 gpio-controller;
463 #gpio-cells = <2>;
464 gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
467 interrupt-controller;
468 #interrupt-cells = <2>;
469 clocks = <&clock HI3620_GPIOCLK16>;
470 clock-names = "apb_pclk";
477 gpio-controller;
478 #gpio-cells = <2>;
479 gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 clocks = <&clock HI3620_GPIOCLK17>;
485 clock-names = "apb_pclk";
492 gpio-controller;
493 #gpio-cells = <2>;
494 gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 clocks = <&clock HI3620_GPIOCLK18>;
500 clock-names = "apb_pclk";
507 gpio-controller;
508 #gpio-cells = <2>;
509 gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
511 interrupt-controller;
512 #interrupt-cells = <2>;
513 clocks = <&clock HI3620_GPIOCLK19>;
514 clock-names = "apb_pclk";
521 gpio-controller;
522 #gpio-cells = <2>;
523 gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 clocks = <&clock HI3620_GPIOCLK20>;
528 clock-names = "apb_pclk";
535 gpio-controller;
536 #gpio-cells = <2>;
537 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
540 clocks = <&clock HI3620_GPIOCLK21>;
541 clock-names = "apb_pclk";
545 compatible = "pinctrl-single";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #pinctrl-cells = <1>;
550 #gpio-range-cells = <3>;
552 pinctrl-single,register-width = <32>;
553 pinctrl-single,function-mask = <7>;
555 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
560 range: gpio-range {
561 #pinctrl-single,gpio-range-cells = <3>;
566 compatible = "pinconf-single";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 #pinctrl-cells = <1>;
572 pinctrl-single,register-width = <32>;