Lines Matching +full:0 +full:x0003b080
23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
199 pinctrl-0 = <&rtc_default_pins>;
204 reg = <0x46000000 0x100>;
217 pinctrl-0 = <&sata_default_pins>;
225 reg = <0x48000000 0x1000>;
233 reg = <0x4b000000 0x100>;
236 pinctrl-0 = <&power_default_pins>;
241 reg = <0x4d000000 0x100>;
253 reg = <0x4e000000 0x100>;
265 reg = <0x4f000000 0x100>;
281 reg = <0x50000000 0x100>;
286 pinctrl-0 = <&pci_default_pins>;
293 interrupt-map-mask = <0xf800 0 0 7>;
295 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
296 <0x4800 0 0 2 &pci_intc 1>,
297 <0x4800 0 0 3 &pci_intc 2>,
298 <0x4800 0 0 4 &pci_intc 3>,
299 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
300 <0x5000 0 0 2 &pci_intc 2>,
301 <0x5000 0 0 3 &pci_intc 3>,
302 <0x5000 0 0 4 &pci_intc 0>,
303 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
304 <0x5800 0 0 2 &pci_intc 3>,
305 <0x5800 0 0 3 &pci_intc 0>,
306 <0x5800 0 0 4 &pci_intc 1>,
307 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
308 <0x6000 0 0 2 &pci_intc 0>,
309 <0x6000 0 0 3 &pci_intc 1>,
310 <0x6000 0 0 4 &pci_intc 2>;
312 bus-range = <0x00 0xff>;
315 /* 1MiB I/O space 0x50000000-0x500fffff */
316 <0x01000000 0 0 0x50000000 0 0x00100000>,
317 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
318 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
322 /* 128MiB at 0x00000000-0x07ffffff */
323 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
324 /* 64MiB at 0x00000000-0x03ffffff */
325 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
326 /* 64MiB at 0x00000000-0x03ffffff */
327 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
337 #address-cells = <0>;
344 reg = <0x60000000 0x4000>, /* Global registers, queue */
345 <0x60004000 0x2000>, /* V-bit */
346 <0x60006000 0x2000>; /* A-bit */
348 pinctrl-0 = <&gmii_default_pins>;
354 gmac0: ethernet-port@0 {
356 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
357 <0x6000a000 0x2000>; /* Port 0 GMAC */
367 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
368 <0x6000e000 0x2000>; /* Port 1 GMAC */
379 reg = <0x62000000 0x10000>;
387 reg = <0x63000000 0x1000>;
395 #size-cells = <0>;
400 reg = <0x63400000 0x1000>;
408 #size-cells = <0>;
414 arm,primecell-periphid = <0x0003b080>;
415 reg = <0x67000000 0x1000>;
430 reg = <0x6a000000 0x1000>;
437 pinctrl-0 = <&tvc_default_pins>;
443 reg = <0x68000000 0x1000>;
457 pinctrl-0 = <&usb_default_pins>;
466 reg = <0x69000000 0x1000>;