Lines Matching +full:hb +full:- +full:sregs
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
20 #address-cells = <1>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 interrupt-parent = <&intc>;
26 compatible = "calxeda,hb-ahci";
29 dma-coherent;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
33 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
35 calxeda,led-order = <4 0 1 2 3>;
39 compatible = "calxeda,hb-sdhci";
51 clock-names = "apb_pclk";
55 #gpio-cells = <2>;
57 gpio-controller;
61 clock-names = "apb_pclk";
66 #gpio-cells = <2>;
68 gpio-controller;
72 clock-names = "apb_pclk";
77 #gpio-cells = <2>;
79 gpio-controller;
83 clock-names = "apb_pclk";
88 #gpio-cells = <2>;
90 gpio-controller;
94 clock-names = "apb_pclk";
103 clock-names = "apb_pclk";
111 clock-names = "apb_pclk";
119 clock-names = "uartclk", "apb_pclk";
123 compatible = "ipmi-smic";
127 reg-size = <4>;
128 reg-spacing = <4>;
131 sregs@fff3c000 {
132 compatible = "calxeda,hb-sregs";
136 #address-cells = <1>;
137 #size-cells = <0>;
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
142 clock-frequency = <33333000>;
146 #clock-cells = <0>;
147 compatible = "calxeda,hb-pll-clock";
153 #clock-cells = <0>;
154 compatible = "calxeda,hb-pll-clock";
160 #clock-cells = <0>;
161 compatible = "calxeda,hb-a9periph-clock";
167 #clock-cells = <0>;
168 compatible = "calxeda,hb-a9bus-clock";
174 #clock-cells = <0>;
175 compatible = "calxeda,hb-pll-clock";
181 #clock-cells = <0>;
182 compatible = "calxeda,hb-emmc-clock";
188 #clock-cells = <0>;
189 compatible = "fixed-clock";
190 clock-frequency = <150000000>;
200 clock-names = "apb_pclk";
204 compatible = "calxeda,hb-xgmac";
207 dma-coherent;
211 compatible = "calxeda,hb-xgmac";
214 dma-coherent;
217 combophy0: combo-phy@fff58000 {
218 compatible = "calxeda,hb-combophy";
219 #phy-cells = <1>;
224 combophy5: combo-phy@fff5d000 {
225 compatible = "calxeda,hb-combophy";
226 #phy-cells = <1>;