Lines Matching +full:0 +full:x4c0
18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
90 ranges = <0 0x81000000 0x8000>;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000>,
98 <0x4000 0x2000>,
99 <0x6000 0x2000>;
109 ranges = <0 0xff800000 0x800000>;
113 reg = <0x480 0x10>;
118 reg = <0x4c0 0x10>;
122 /* GPIOs 0 .. 31 */
125 reg = <0x500 0x04>, <0x520 0x04>;
135 reg = <0x504 0x04>, <0x524 0x04>;
145 reg = <0x508 0x04>, <0x528 0x04>;
155 reg = <0x50c 0x04>, <0x52c 0x04>;
165 reg = <0x510 0x04>, <0x530 0x04>;
175 reg = <0x514 0x04>, <0x534 0x04>;
185 reg = <0x518 0x04>, <0x538 0x04>;
195 reg = <0x51c 0x04>, <0x53c 0x04>;
204 reg = <0xb80 0x28>;
210 #size-cells = <0>;
212 reg = <0x700 0xdc>;
218 #size-cells = <0>;
219 compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0";
220 reg = <0x1000 0x600>;
230 #size-cells = <0>;
232 reg = <0x1800 0x600>, <0x2000 0x10>;
236 nandcs: nand@0 {
238 reg = <0>;
245 arm,primecell-periphid = <0x00041081>;
246 reg = <0x11000 0x1000>;
257 reg = <0x12000 0x1000>;