Lines Matching +full:sata3 +full:- +full:ahci
1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
30 enable-method = "brcm,bcm63138";
35 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
38 enable-method = "brcm,bcm63138";
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <50000000>;
49 clock-output-names = "periph";
54 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
57 clock-div = <2>;
58 clock-mult = <1>;
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
66 clock-div = <4>;
67 clock-mult = <1>;
70 hsspi_pll: hsspi-pll {
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <400000000>;
79 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
84 L2: cache-controller@1d000 {
85 compatible = "arm,pl310-cache";
87 cache-unified;
88 cache-level = <2>;
89 cache-size = <524288>;
90 cache-sets = <1024>;
91 cache-line-size = <32>;
96 compatible = "arm,cortex-a9-scu";
100 gic: interrupt-controller@1f000 {
101 compatible = "arm,cortex-a9-gic";
104 #interrupt-cells = <3>;
105 #address-cells = <0>;
106 interrupt-controller;
110 compatible = "arm,cortex-a9-global-timer";
116 local_timer: local-timer@1e600 {
117 compatible = "arm,cortex-a9-twd-timer";
125 compatible = "arm,cortex-a9-twd-wdt";
132 #clock-cells = <0>;
133 compatible = "brcm,bcm63138-armpll";
138 pmb0: reset-controller@4800c0 {
139 compatible = "brcm,bcm63138-pmb";
141 #reset-cells = <2>;
144 pmb1: reset-controller@4800e0 {
145 compatible = "brcm,bcm63138-pmb";
147 #reset-cells = <2>;
150 ahci: sata@a000 {
151 compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
152 reg-names = "ahci", "top-ctrl";
155 #address-cells = <1>;
156 #size-cells = <0>;
158 reset-names = "ahci";
161 sata0: sata-port@0 {
167 sata_phy: sata-phy@8100 {
168 compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
170 reg-names = "phy";
171 #address-cells = <1>;
172 #size-cells = <0>;
175 sata_phy0: sata-phy@0 {
177 #phy-cells = <0>;
184 compatible = "simple-bus";
185 #address-cells = <1>;
186 #size-cells = <1>;
190 compatible = "brcm,bcm6328-timer", "syscon";
195 compatible = "brcm,bcm6345-uart";
199 clock-names = "periph";
204 compatible = "brcm,bcm6345-uart";
208 clock-names = "periph";
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0";
219 clock-names = "hsspi", "pll";
220 num-cs = <8>;
224 nand_controller: nand-controller@2000 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
229 reg-names = "nand", "nand-int-base";
232 interrupt-names = "nand";
236 compatible = "brcm,bcm63138-hs-uart", "brcm,bcmbca-hs-uart";
242 compatible = "brcm,bcm63138-bootlut";
247 compatible = "syscon-reboot";