Lines Matching +full:0 +full:x7e202000
11 /memreserve/ 0x00000000 0x00001000;
40 size = <0x4000000>; /* 64MB */
48 polling-delay-passive = <0>;
54 hysteresis = <0>;
71 reg = <0x7e003000 0x1000>;
72 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
82 reg = <0x7e004000 0x20>;
89 reg = <0x7e101000 0x2000>;
96 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
97 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
102 reg = <0x7e00b880 0x40>;
103 interrupts = <0 1>;
104 #mbox-cells = <0>;
109 reg = <0x7e200000 0xb4>;
129 gpio-ranges = <&gpio 0 0 54>;
139 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
190 brcm,pins = <0 1>;
306 reg = <0x7e201000 0x200>;
311 arm,primecell-periphid = <0x00241011>;
316 reg = <0x7e202000 0x100>;
324 reg = <0x7e203000 0x24>;
331 reg = <0x7e204000 0x200>;
335 #size-cells = <0>;
341 reg = <0x7e205000 0x200>;
345 #size-cells = <0>;
351 reg = <0x7e208000 0x8c>;
360 reg = <0x7e209000 0x78>;
363 #size-cells = <0>;
381 reg = <0x7e215000 0x8>;
387 reg = <0x7e215040 0x40>;
395 reg = <0x7e215080 0x40>;
399 #size-cells = <0>;
405 reg = <0x7e2150c0 0x40>;
409 #size-cells = <0>;
415 reg = <0x7e20c000 0x28>;
425 reg = <0x7e300000 0x100>;
433 reg = <0x7e400000 0x6000>;
439 reg = <0x7e700000 0x8c>;
442 #size-cells = <0>;
459 reg = <0x7e804000 0x1000>;
463 #size-cells = <0>;
469 reg = <0x7e980000 0x10000>;
472 #size-cells = <0>;
484 #clock-cells = <0>;
491 #clock-cells = <0>;
499 #phy-cells = <0>;