Lines Matching +full:1 +full:kib

11 	#size-cells = <1>;
105 			#dma-cells = <1>;
111 			#power-domain-cells = <1>;
112 			#reset-cells = <1>;
179 			#address-cells = <1>;
189 			#address-cells = <1>;
199 			#address-cells = <1>;
209 			#address-cells = <1>;
219 			#address-cells = <1>;
229 			#address-cells = <1>;
239 			#address-cells = <1>;
249 			#address-cells = <1>;
317 			#clock-cells = <1>;
318 			#reset-cells = <1>;
326 			#interrupt-cells = <1>;
352 			interrupts = <0>, <1>, <2>,
392 			resets = <&dvp 1>;
421 		#size-cells = <1>;
459 		#address-cells = <1>;
465 		 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
478 			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
481 			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
485 		cpu1: cpu@1 {
488 			reg = <1>;
493 			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
496 			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
508 			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
511 			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
523 			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
526 			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
542 			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
550 		#size-cells = <1>;
560 			#interrupt-cells = <1>;
566 			interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
610 			#address-cells = <1>;
879 	pwm0_1_gpio13: pwm0-1-gpio13 {
886 	pwm0_1_gpio19: pwm0-1-gpio19 {
893 	pwm1_1_gpio41: pwm1-1-gpio41 {
900 	pwm0_1_gpio45: pwm0-1-gpio45 {
914 	pwm0_1_gpio53: pwm0-1-gpio53 {
1129 	 * only address the lower 1G of memory (ZONE_DMA).