Lines Matching +full:0 +full:xf01
55 #size-cells = <0>;
57 cpu0: cpu@0 {
60 reg = <0>;
74 reg = <0xf8000000 0x48>;
80 psci_version = <0x84000000>;
81 cpu_on = <0x84000003>;
82 system_reset = <0x84000009>;
87 reg = <0xfaf00000 0x58>;
92 #clock-cells = <0>;
98 #clock-cells = <0>;
106 reg = <0xf8000000 0x48>;
113 reg = <0xfaf00200 0x20>;
114 interrupts = <GIC_PPI 11 0xf01>;
120 reg = <0xfaf00600 0x20>;
121 interrupts = <GIC_PPI 13 0xf04>;
130 reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
137 reg = <0xfaf10000 0x1000>;
141 arm,filter-ranges = <0x0 0x80000000>;
143 arm,double-linefill-incr = <0>;
144 arm,double-linefill-wrap = <0>;
147 arm,prefetch-offset = <0>;
153 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
164 reg = <0xf8050000 0x2000
165 0xf8040000 0x1000
166 0xc0000000 0x2000>;
172 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
174 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
176 bus-range = <0x00 0xff>;
180 interrupt-map-mask = <0 0 0 0x7>;
181 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
184 <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
191 reg = <0xf8050000 0x2000
192 0xf8051000 0x2000
193 0xf8040000 0x1000
194 0xc0000000 0x20000000>;
205 reg = <0xf801d000 0x400>;
229 amba@0 {
231 #address-cells = <0x1>;
232 #size-cells = <0x1>;
238 reg = <0xf4264000 0x4000>;
244 reg = <0xf8019000 0x400>;
266 reg = <0xf8019400 0x400>;
295 reg = <0xf8010000 0x4000>;
316 snps,blen = <0 0 0 0 16 0 0>;
333 reg = <0xf8036000 0x1000>;
339 pinctrl-0 = <&pinctrl_uart0>;
347 reg = <0xf8037000 0x1000>;
353 pinctrl-0 = <&pinctrl_uart1>;
361 reg = <0xf8038000 0x1000>;
367 pinctrl-0 = <&pinctrl_uart2>;
368 dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
375 reg = <0xf8039000 0x1000>;
381 pinctrl-0 = <&pinctrl_uart3>;