Lines Matching +full:cpu +full:- +full:offset
23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb11mp";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "arm,realview-smp";
56 MP11_0: cpu@0 {
57 device_type = "cpu";
60 next-level-cache = <&L2>;
63 MP11_1: cpu@1 {
64 device_type = "cpu";
67 next-level-cache = <&L2>;
70 MP11_2: cpu@2 {
71 device_type = "cpu";
74 next-level-cache = <&L2>;
77 MP11_3: cpu@3 {
78 device_type = "cpu";
81 next-level-cache = <&L2>;
85 /* Primary TestChip GIC synthesized with the CPU */
86 intc_tc11mp: interrupt-controller@1f000100 {
87 compatible = "arm,tc11mp-gic";
88 #interrupt-cells = <3>;
89 #address-cells = <1>;
90 interrupt-controller;
95 L2: cache-controller@1f002000 {
96 compatible = "arm,l220-cache";
98 interrupt-parent = <&intc_tc11mp>;
102 cache-unified;
103 cache-level = <2>;
111 cache-size = <1048576>; // 1MB
112 cache-sets = <4096>;
113 cache-line-size = <32>;
114 arm,shared-override;
115 arm,parity-enable;
116 arm,outer-sync-disable;
120 compatible = "arm,arm11mp-scu";
125 compatible = "arm,arm11mp-twd-timer";
127 interrupt-parent = <&intc_tc11mp>;
132 compatible = "arm,arm11mp-twd-wdt";
134 interrupt-parent = <&intc_tc11mp>;
140 compatible = "arm,arm11mpcore-pmu";
141 interrupt-parent = <&intc_tc11mp>;
146 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
150 vmmc: regulator-vmmc {
151 compatible = "regulator-fixed";
152 regulator-name = "vmmc";
153 regulator-min-microvolt = <3300000>;
154 regulator-max-microvolt = <3300000>;
155 regulator-boot-on;
158 veth: regulator-veth {
159 compatible = "regulator-fixed";
160 regulator-name = "veth";
161 regulator-min-microvolt = <3300000>;
162 regulator-max-microvolt = <3300000>;
163 regulator-boot-on;
166 xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
167 #clock-cells = <0>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
172 refclk32khz: clock-32768 {
173 compatible = "fixed-clock";
174 #clock-cells = <0>;
175 clock-frequency = <32768>;
178 timclk: clock-1000000 {
179 #clock-cells = <0>;
180 compatible = "fixed-factor-clock";
181 clock-div = <24>;
182 clock-mult = <1>;
187 pclk: clock-pclk {
188 #clock-cells = <0>;
189 compatible = "fixed-clock";
190 clock-frequency = <0>;
195 compatible = "arm,versatile-flash", "cfi-flash";
197 bank-width = <4>;
199 compatible = "arm,arm-firmware-suite";
205 compatible = "arm,versatile-flash", "cfi-flash";
207 bank-width = <4>;
209 compatible = "arm,arm-firmware-suite";
215 #address-cells = <1>;
216 #size-cells = <0>;
219 #address-cells = <1>;
220 #size-cells = <0>;
226 remote-endpoint = <&clcd_pads>;
234 remote-endpoint = <&vga_con_in>;
246 compatible = "vga-connector";
247 ddc-i2c-bus = <&i2c1>;
251 remote-endpoint = <&vga_bridge_out>;
257 #address-cells = <1>;
258 #size-cells = <1>;
259 compatible = "arm,realview-pb11mp-soc", "simple-bus";
264 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
267 #address-cells = <1>;
268 #size-cells = <1>;
271 compatible = "register-bit-led";
273 offset = <0x08>;
276 linux,default-trigger = "heartbeat";
277 default-state = "on";
280 compatible = "register-bit-led";
282 offset = <0x08>;
285 linux,default-trigger = "mmc0";
286 default-state = "off";
289 compatible = "register-bit-led";
291 offset = <0x08>;
294 linux,default-trigger = "cpu0";
295 default-state = "off";
298 compatible = "register-bit-led";
300 offset = <0x08>;
303 linux,default-trigger = "cpu1";
304 default-state = "off";
307 compatible = "register-bit-led";
309 offset = <0x08>;
312 linux,default-trigger = "cpu2";
313 default-state = "off";
316 compatible = "register-bit-led";
318 offset = <0x08>;
321 linux,default-trigger = "cpu3";
322 default-state = "off";
325 compatible = "register-bit-led";
327 offset = <0x08>;
330 default-state = "off";
333 compatible = "register-bit-led";
335 offset = <0x08>;
338 default-state = "off";
341 oscclk0: clock-controller@c {
342 compatible = "arm,syscon-icst307";
344 #clock-cells = <0>;
345 lock-offset = <0x20>;
346 vco-offset = <0x0C>;
349 oscclk1: clock-controller@10 {
350 compatible = "arm,syscon-icst307";
352 #clock-cells = <0>;
353 lock-offset = <0x20>;
354 vco-offset = <0x10>;
357 oscclk2: clock-controller@14 {
358 compatible = "arm,syscon-icst307";
360 #clock-cells = <0>;
361 lock-offset = <0x20>;
362 vco-offset = <0x14>;
365 oscclk3: clock-controller@18 {
366 compatible = "arm,syscon-icst307";
368 #clock-cells = <0>;
369 lock-offset = <0x20>;
370 vco-offset = <0x18>;
373 oscclk4: clock-controller@1c {
374 compatible = "arm,syscon-icst307";
376 #clock-cells = <0>;
377 lock-offset = <0x20>;
378 vco-offset = <0x1c>;
381 oscclk5: clock-controller@d4 {
382 compatible = "arm,syscon-icst307";
384 #clock-cells = <0>;
385 lock-offset = <0x20>;
386 vco-offset = <0xd4>;
389 oscclk6: clock-controller@d8 {
390 compatible = "arm,syscon-icst307";
392 #clock-cells = <0>;
393 lock-offset = <0x20>;
394 vco-offset = <0xd8>;
403 clock-names = "refclk", "timclk", "apb_pclk";
404 #clock-cells = <1>;
405 clock-output-names = "timerclk0",
409 assigned-clocks = <&sp810_syscon 0>,
413 assigned-clock-parents = <&timclk>,
420 #address-cells = <1>;
421 #size-cells = <0>;
422 compatible = "arm,versatile-i2c";
434 interrupt-parent = <&intc_tc11mp>;
437 clock-names = "apb_pclk";
443 interrupt-parent = <&intc_tc11mp>;
447 max-frequency = <500000>;
448 bus-width = <4>;
449 cap-sd-highspeed;
450 cap-mmc-highspeed;
452 clock-names = "mclk", "apb_pclk";
453 vmmc-supply = <&vmmc>;
454 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
455 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
461 interrupt-parent = <&intc_tc11mp>;
464 clock-names = "KMIREFCLK", "apb_pclk";
470 interrupt-parent = <&intc_tc11mp>;
473 clock-names = "KMIREFCLK", "apb_pclk";
479 interrupt-parent = <&intc_tc11mp>;
482 clock-names = "uartclk", "apb_pclk";
488 interrupt-parent = <&intc_tc11mp>;
491 clock-names = "uartclk", "apb_pclk";
497 interrupt-parent = <&intc_pb11mp>;
500 clock-names = "uartclk", "apb_pclk";
506 interrupt-parent = <&intc_pb11mp>;
509 clock-names = "uartclk", "apb_pclk";
515 interrupt-parent = <&intc_pb11mp>;
518 clock-names = "sspclk", "apb_pclk";
524 interrupt-parent = <&intc_pb11mp>;
527 clock-names = "wdog_clk", "apb_pclk";
534 interrupt-parent = <&intc_pb11mp>;
537 clock-names = "wdog_clk", "apb_pclk";
543 interrupt-parent = <&intc_tc11mp>;
545 arm,sp804-has-irq = <1>;
549 clock-names = "timer0clk",
557 interrupt-parent = <&intc_tc11mp>;
559 arm,sp804-has-irq = <1>;
563 clock-names = "timer0clk",
571 gpio-controller;
572 interrupt-parent = <&intc_pb11mp>;
574 #gpio-cells = <2>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
578 clock-names = "apb_pclk";
584 gpio-controller;
585 interrupt-parent = <&intc_pb11mp>;
587 #gpio-cells = <2>;
588 interrupt-controller;
589 #interrupt-cells = <2>;
591 clock-names = "apb_pclk";
597 gpio-controller;
598 interrupt-parent = <&intc_pb11mp>;
600 #gpio-cells = <2>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
604 clock-names = "apb_pclk";
608 #address-cells = <1>;
609 #size-cells = <0>;
610 compatible = "arm,versatile-i2c";
617 interrupt-parent = <&intc_tc11mp>;
620 clock-names = "apb_pclk";
627 clock-names = "timer0clk", "timer1clk", "apb_pclk";
635 clock-names = "timer0clk", "timer1clk", "apb_pclk";
643 interrupt-parent = <&intc_pb11mp>;
644 interrupt-names = "combined";
647 clock-names = "clcdclk", "apb_pclk";
649 max-memory-bandwidth = <95000000>;
653 remote-endpoint = <&vga_bridge_in>;
654 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
663 intc_pb11mp: interrupt-controller@1e000000 {
664 compatible = "arm,arm11mp-gic";
665 #interrupt-cells = <3>;
666 #address-cells = <1>;
667 interrupt-controller;
670 interrupt-parent = <&intc_tc11mp>;
678 interrupt-parent = <&intc_tc11mp>;
680 phy-mode = "mii";
681 reg-io-width = <4>;
682 smsc,irq-active-high;
683 smsc,irq-push-pull;
684 vdd33a-supply = <&veth>;
685 vddvario-supply = <&veth>;
689 compatible = "nxp,usb-isp1761";
691 interrupt-parent = <&intc_tc11mp>;