Lines Matching +full:0 +full:x1000a000
45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
53 #size-cells = <0>;
56 MP11_0: cpu@0 {
59 reg = <0>;
91 reg = <0x1f001000 0x1000>,
92 <0x1f000100 0x100>;
97 reg = <0x1f002000 0x1000>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
100 <0 30 IRQ_TYPE_LEVEL_HIGH>,
101 <0 31 IRQ_TYPE_LEVEL_HIGH>;
121 reg = <0x1f000000 0x100>;
126 reg = <0x1f000600 0x20>;
128 interrupts = <1 13 0xf04>;
133 reg = <0x1f000620 0x20>;
135 interrupts = <1 14 0xf04>;
142 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
143 <0 18 IRQ_TYPE_LEVEL_HIGH>,
144 <0 19 IRQ_TYPE_LEVEL_HIGH>,
145 <0 20 IRQ_TYPE_LEVEL_HIGH>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
179 #clock-cells = <0>;
187 #clock-cells = <0>;
195 #clock-cells = <0>;
203 #clock-cells = <0>;
211 #clock-cells = <0>;
219 #clock-cells = <0>;
227 pclk: pclk@0 {
228 #clock-cells = <0>;
230 clock-frequency = <0>;
236 reg = <0x40000000 0x04000000>;
246 reg = <0x44000000 0x04000000>;
256 #size-cells = <0>;
260 #size-cells = <0>;
262 port@0 {
263 reg = <0>;
305 reg = <0x10000000 0x1000>;
306 ranges = <0x0 0x10000000 0x1000>;
310 led@8,0 {
312 reg = <0x08 0x04>;
313 offset = <0x08>;
314 mask = <0x01>;
315 label = "versatile:0";
321 reg = <0x08 0x04>;
322 offset = <0x08>;
323 mask = <0x02>;
330 reg = <0x08 0x04>;
331 offset = <0x08>;
332 mask = <0x04>;
339 reg = <0x08 0x04>;
340 offset = <0x08>;
341 mask = <0x08>;
348 reg = <0x08 0x04>;
349 offset = <0x08>;
350 mask = <0x10>;
357 reg = <0x08 0x04>;
358 offset = <0x08>;
359 mask = <0x20>;
366 reg = <0x08 0x04>;
367 offset = <0x08>;
368 mask = <0x40>;
374 reg = <0x08 0x04>;
375 offset = <0x08>;
376 mask = <0x80>;
383 reg = <0x0c 0x04>;
384 #clock-cells = <0>;
385 lock-offset = <0x20>;
386 vco-offset = <0x0C>;
391 reg = <0x10 0x04>;
392 #clock-cells = <0>;
393 lock-offset = <0x20>;
394 vco-offset = <0x10>;
399 reg = <0x14 0x04>;
400 #clock-cells = <0>;
401 lock-offset = <0x20>;
402 vco-offset = <0x14>;
407 reg = <0x18 0x04>;
408 #clock-cells = <0>;
409 lock-offset = <0x20>;
410 vco-offset = <0x18>;
415 reg = <0x1c 0x04>;
416 #clock-cells = <0>;
417 lock-offset = <0x20>;
418 vco-offset = <0x1c>;
423 reg = <0xd4 0x04>;
424 #clock-cells = <0>;
425 lock-offset = <0x20>;
426 vco-offset = <0xd4>;
431 reg = <0xd8 0x04>;
432 #clock-cells = <0>;
433 lock-offset = <0x20>;
434 vco-offset = <0xd8>;
441 reg = <0x10001000 0x1000>;
449 assigned-clocks = <&sp810_syscon 0>,
461 #size-cells = <0>;
463 reg = <0x10002000 0x1000>;
467 reg = <0x68>;
473 reg = <0x10004000 0x1000>;
475 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
482 reg = <0x10005000 0x1000>;
484 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
485 <0 15 IRQ_TYPE_LEVEL_HIGH>;
494 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
500 reg = <0x10006000 0x1000>;
502 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
509 reg = <0x10007000 0x1000>;
511 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
518 reg = <0x10009000 0x1000>;
520 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
527 reg = <0x1000a000 0x1000>;
529 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
536 reg = <0x1000b000 0x1000>;
538 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
545 reg = <0x1000c000 0x1000>;
547 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
554 reg = <0x1000d000 0x1000>;
556 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
563 reg = <0x1000f000 0x1000>;
565 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
573 reg = <0x10010000 0x1000>;
575 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
582 reg = <0x10011000 0x1000>;
584 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&sp810_syscon 0>,
596 reg = <0x10012000 0x1000>;
598 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
610 reg = <0x10013000 0x1000>;
613 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
623 reg = <0x10014000 0x1000>;
626 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
636 reg = <0x10015000 0x1000>;
639 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
649 #size-cells = <0>;
651 reg = <0x10016000 0x1000>;
656 reg = <0x10017000 0x1000>;
658 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
665 reg = <0x10018000 0x1000>;
673 reg = <0x10019000 0x1000>;
682 reg = <0x10020000 0x1000>;
685 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
694 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
708 reg = <0x1e001000 0x1000>,
709 <0x1e000000 0x100>;
711 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
717 reg = <0x4e000000 0x10000>;
719 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
730 reg = <0x4f000000 0x20000>;
732 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;