Lines Matching +full:0 +full:x10006000

45 		 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 		 * and the first 256 are also remapped @ 0x00000000
48 		reg = <0x70000000 0x20000000>;
53 		#size-cells = <0>;
56 		MP11_0: cpu@0 {
59 			reg = <0>;
91 		reg = <0x1f001000 0x1000>,
92 		      <0x1f000100 0x100>;
97 		reg = <0x1f002000 0x1000>;
99 		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
100 			     <0 30 IRQ_TYPE_LEVEL_HIGH>,
101 			     <0 31 IRQ_TYPE_LEVEL_HIGH>;
121 		reg = <0x1f000000 0x100>;
126 		reg = <0x1f000600 0x20>;
128 		interrupts = <1 13 0xf04>;
133 		reg = <0x1f000620 0x20>;
135 		interrupts = <1 14 0xf04>;
142 		interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
143 			     <0 18 IRQ_TYPE_LEVEL_HIGH>,
144 			     <0 19 IRQ_TYPE_LEVEL_HIGH>,
145 			     <0 20 IRQ_TYPE_LEVEL_HIGH>;
167 		#clock-cells = <0>;
174 		#clock-cells = <0>;
179 		#clock-cells = <0>;
188 		#clock-cells = <0>;
190 		clock-frequency = <0>;
196 		reg = <0x40000000 0x04000000>;
206 		reg = <0x44000000 0x04000000>;
216 		#size-cells = <0>;
220 			#size-cells = <0>;
222 			port@0 {
223 				reg = <0>;
265 			reg = <0x10000000 0x1000>;
266 			ranges = <0x0 0x10000000 0x1000>;
270 			led@8,0 {
272 				reg = <0x08 0x04>;
273 				offset = <0x08>;
274 				mask = <0x01>;
275 				label = "versatile:0";
281 				reg = <0x08 0x04>;
282 				offset = <0x08>;
283 				mask = <0x02>;
290 				reg = <0x08 0x04>;
291 				offset = <0x08>;
292 				mask = <0x04>;
299 				reg = <0x08 0x04>;
300 				offset = <0x08>;
301 				mask = <0x08>;
308 				reg = <0x08 0x04>;
309 				offset = <0x08>;
310 				mask = <0x10>;
317 				reg = <0x08 0x04>;
318 				offset = <0x08>;
319 				mask = <0x20>;
326 				reg = <0x08 0x04>;
327 				offset = <0x08>;
328 				mask = <0x40>;
334 				reg = <0x08 0x04>;
335 				offset = <0x08>;
336 				mask = <0x80>;
343 				reg = <0x0c 0x04>;
344 				#clock-cells = <0>;
345 				lock-offset = <0x20>;
346 				vco-offset = <0x0C>;
351 				reg = <0x10 0x04>;
352 				#clock-cells = <0>;
353 				lock-offset = <0x20>;
354 				vco-offset = <0x10>;
359 				reg = <0x14 0x04>;
360 				#clock-cells = <0>;
361 				lock-offset = <0x20>;
362 				vco-offset = <0x14>;
367 				reg = <0x18 0x04>;
368 				#clock-cells = <0>;
369 				lock-offset = <0x20>;
370 				vco-offset = <0x18>;
375 				reg = <0x1c 0x04>;
376 				#clock-cells = <0>;
377 				lock-offset = <0x20>;
378 				vco-offset = <0x1c>;
383 				reg = <0xd4 0x04>;
384 				#clock-cells = <0>;
385 				lock-offset = <0x20>;
386 				vco-offset = <0xd4>;
391 				reg = <0xd8 0x04>;
392 				#clock-cells = <0>;
393 				lock-offset = <0x20>;
394 				vco-offset = <0xd8>;
401 			reg = <0x10001000 0x1000>;
409 			assigned-clocks = <&sp810_syscon 0>,
421 			#size-cells = <0>;
423 			reg = <0x10002000 0x1000>;
427 				reg = <0x68>;
433 			reg = <0x10004000 0x1000>;
435 			interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
442 			reg = <0x10005000 0x1000>;
444 			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
445 					<0 15 IRQ_TYPE_LEVEL_HIGH>;
454 			cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
460 			reg = <0x10006000 0x1000>;
462 			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
469 			reg = <0x10007000 0x1000>;
471 			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
478 			reg = <0x10009000 0x1000>;
480 			interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
487 			reg = <0x1000a000 0x1000>;
489 			interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
496 			reg = <0x1000b000 0x1000>;
498 			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
505 			reg = <0x1000c000 0x1000>;
507 			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
514 			reg = <0x1000d000 0x1000>;
516 			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
523 			reg = <0x1000f000 0x1000>;
525 			interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
533 			reg = <0x10010000 0x1000>;
535 			interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
542 			reg = <0x10011000 0x1000>;
544 			interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
546 			clocks = <&sp810_syscon 0>,
556 			reg = <0x10012000 0x1000>;
558 			interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
570 			reg = <0x10013000 0x1000>;
573 			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
583 			reg = <0x10014000 0x1000>;
586 			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
596 			reg = <0x10015000 0x1000>;
599 			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
609 			#size-cells = <0>;
611 			reg = <0x10016000 0x1000>;
616 			reg = <0x10017000 0x1000>;
618 			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
625 			reg = <0x10018000 0x1000>;
633 			reg = <0x10019000 0x1000>;
642 			reg = <0x10020000 0x1000>;
645 			interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
654 					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
668 			reg = <0x1e001000 0x1000>,
669 			      <0x1e000000 0x100>;
671 			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
677 			reg = <0x4e000000 0x10000>;
679 			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
690 			reg = <0x4f000000 0x20000>;
692 			interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;