Lines Matching full:clkc

7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
27 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
29 			clocks = <&clkc CLKID_CPUCLK>;
39 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
41 			clocks = <&clkc CLKID_CPUCLK>;
51 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
53 			clocks = <&clkc CLKID_CPUCLK>;
63 			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
65 			clocks = <&clkc CLKID_CPUCLK>;
231 			compatible = "amlogic,meson8b-ddr-clkc";
274 			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
284 	clocks = <&clkc CLKID_AIU_GLUE>,
285 		 <&clkc CLKID_I2S_OUT>,
286 		 <&clkc CLKID_AOCLK_GATE>,
287 		 <&clkc CLKID_CTS_AMCLK>,
288 		 <&clkc CLKID_MIXER_IFACE>,
289 		 <&clkc CLKID_IEC958>,
290 		 <&clkc CLKID_IEC958_GATE>,
291 		 <&clkc CLKID_CTS_MCLK_I958>,
292 		 <&clkc CLKID_CTS_I958>;
391 	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
553 	clocks = <&clkc CLKID_EFUSE>;
568 	clocks = <&clkc CLKID_ETH>,
569 		 <&clkc CLKID_MPLL2>,
570 		 <&clkc CLKID_MPLL2>,
571 		 <&clkc CLKID_FCLK_DIV2>;
589 	clkc: clock-controller {  label
590 		compatible = "amlogic,meson8b-clkc";
615 		clocks = <&clkc CLKID_VPU>;
617 		assigned-clocks = <&clkc CLKID_VPU>;
624 	clocks = <&clkc CLKID_RNG0>;
629 	clocks = <&clkc CLKID_CLK81>;
633 	clocks = <&clkc CLKID_I2C>;
637 	clocks = <&clkc CLKID_I2C>;
662 		clocks = <&clkc CLKID_PERIPH>;
675 		clocks = <&clkc CLKID_PERIPH>;
694 	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
704 		 <&clkc CLKID_FCLK_DIV4>,
705 		 <&clkc CLKID_FCLK_DIV3>,
706 		 <&clkc CLKID_FCLK_DIV5>,
707 		 <&clkc CLKID_SDHC>;
720 	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
725 	clocks = <&xtal>, <&clkc CLKID_CLK81>;
731 	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
737 	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
743 	clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
749 	clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
755 	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
761 	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
767 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
774 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;