Lines Matching full:clkc

6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
29 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
31 			clocks = <&clkc CLKID_CPUCLK>;
41 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
43 			clocks = <&clkc CLKID_CPUCLK>;
53 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
55 			clocks = <&clkc CLKID_CPUCLK>;
65 			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
67 			clocks = <&clkc CLKID_CPUCLK>;
254 			compatible = "amlogic,meson8-ddr-clkc";
308 			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
311 			assigned-clocks = <&clkc CLKID_MALI>;
322 	clocks = <&clkc CLKID_AIU_GLUE>,
323 		 <&clkc CLKID_I2S_OUT>,
324 		 <&clkc CLKID_AOCLK_GATE>,
325 		 <&clkc CLKID_CTS_AMCLK>,
326 		 <&clkc CLKID_MIXER_IFACE>,
327 		 <&clkc CLKID_IEC958>,
328 		 <&clkc CLKID_IEC958_GATE>,
329 		 <&clkc CLKID_CTS_MCLK_I958>,
330 		 <&clkc CLKID_CTS_I958>;
437 	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
606 	clocks = <&clkc CLKID_EFUSE>;
616 	clocks = <&clkc CLKID_ETH>;
628 	clkc: clock-controller {  label
629 		compatible = "amlogic,meson8-clkc";
640 		clocks = <&clkc CLKID_VPU>;
642 		assigned-clocks = <&clkc CLKID_VPU>;
649 	clocks = <&clkc CLKID_RNG0>;
654 	clocks = <&clkc CLKID_CLK81>;
658 	clocks = <&clkc CLKID_CLK81>;
662 	clocks = <&clkc CLKID_CLK81>;
687 		clocks = <&clkc CLKID_PERIPH>;
700 		clocks = <&clkc CLKID_PERIPH>;
719 	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
729 		 <&clkc CLKID_FCLK_DIV4>,
730 		 <&clkc CLKID_FCLK_DIV3>,
731 		 <&clkc CLKID_FCLK_DIV5>,
732 		 <&clkc CLKID_SDHC>;
745 	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
750 	clocks = <&clkc CLKID_CLK81>;
754 	clocks = <&xtal>, <&clkc CLKID_CLK81>;
760 	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
766 	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
772 	clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
778 	clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
784 	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
790 	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
796 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
803 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;