Lines Matching +full:0 +full:x08001454
65 #size-cells = <0>;
67 cpu0: cpu@0 {
73 reg = <0x0>;
82 reg = <0x1>;
91 reg = <0x2>;
100 reg = <0x3>;
109 reg = <0x100>;
118 reg = <0x101>;
127 reg = <0x102>;
136 reg = <0x103>;
157 ranges = <0 0 0 0x20000000>;
171 #clock-cells = <0>;
183 #clock-cells = <0>;
200 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
216 reg = <0x00800030 0x4>;
223 reg = <0x08001410 0x4>;
224 #clock-cells = <0>;
233 #clock-cells = <0>;
242 reg = <0x0800141c 0x4>;
243 #clock-cells = <0>;
250 reg = <0x08001428 0x4>;
253 clock-indices = <0>, <1>,
270 reg = <0x08001450 0x4>;
271 #clock-cells = <0>;
278 reg = <0x08001454 0x4>;
279 #clock-cells = <0>;
300 ranges = <0 0 0 0x20000000>;
303 /* 256 KiB secure SRAM at 0x20000 */
305 reg = <0x00020000 0x40000>;
309 ranges = <0 0x00020000 0x40000>;
317 reg = <0x1000 0x8>;
323 reg = <0x00830000 0x1054>;
338 #size-cells = <0>;
344 reg = <0x00a00000 0x100>;
355 reg = <0x00a00400 0x100>;
367 reg = <0x00a00800 0x4>;
373 #phy-cells = <0>;
378 reg = <0x00a01000 0x100>;
389 reg = <0x00a01800 0x4>;
401 #phy-cells = <0>;
408 reg = <0x00a02000 0x100>;
419 reg = <0x00a02400 0x100>;
431 reg = <0x00a02800 0x4>;
443 #phy-cells = <0>;
448 reg = <0x00a08000 0x8>;
457 reg = <0x01700000 0x100>;
462 reg = <0x01c02000 0x1000>;
471 reg = <0x01c0f000 0x1000>;
472 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
476 resets = <&mmc_config_clk 0>;
481 #size-cells = <0>;
486 reg = <0x01c10000 0x1000>;
496 #size-cells = <0>;
501 reg = <0x01c11000 0x1000>;
511 #size-cells = <0>;
516 reg = <0x01c12000 0x1000>;
526 #size-cells = <0>;
531 reg = <0x01c13000 0x10>;
542 reg = <0x01c41000 0x1000>,
543 <0x01c42000 0x2000>,
544 <0x01c44000 0x2000>,
545 <0x01c46000 0x2000>;
555 reg = <0x01c90000 0x1000>;
556 ranges = <0x0 0x01c90000 0x10000>;
561 reg = <0x4000 0x1000>;
567 reg = <0x5000 0x1000>;
572 reg = <0x9000 0x5000>;
583 reg = <0x03000000 0x30>;
597 reg = <0x03100000 0x40000>;
607 #size-cells = <0>;
621 reg = <0x03140000 0x40000>;
631 #size-cells = <0>;
645 reg = <0x03200000 0x40000>;
655 #size-cells = <0>;
657 be0_in: port@0 {
659 #size-cells = <0>;
660 reg = <0>;
662 be0_in_deu0: endpoint@0 {
663 reg = <0>;
685 reg = <0x03240000 0x40000>;
695 #size-cells = <0>;
697 be1_in: port@0 {
699 #size-cells = <0>;
700 reg = <0>;
702 be1_in_deu0: endpoint@0 {
703 reg = <0>;
725 reg = <0x03300000 0x40000>;
737 #size-cells = <0>;
739 deu0_in: port@0 {
740 reg = <0>;
749 #size-cells = <0>;
752 deu0_out_be0: endpoint@0 {
753 reg = <0>;
767 reg = <0x03340000 0x40000>;
779 #size-cells = <0>;
781 deu1_in: port@0 {
782 reg = <0>;
791 #size-cells = <0>;
794 deu1_out_be0: endpoint@0 {
795 reg = <0>;
809 reg = <0x03400000 0x40000>;
821 #size-cells = <0>;
823 drc0_in: port@0 {
824 reg = <0>;
843 reg = <0x03440000 0x40000>;
855 #size-cells = <0>;
857 drc1_in: port@0 {
858 reg = <0>;
877 reg = <0x03c00000 0x10000>;
888 #clock-cells = <0>;
892 #size-cells = <0>;
894 tcon0_in: port@0 {
895 reg = <0>;
910 reg = <0x03c10000 0x10000>;
919 #size-cells = <0>;
921 tcon1_in: port@0 {
922 reg = <0>;
937 reg = <0x06000000 0x800>;
946 reg = <0x06000c00 0xa0>;
959 reg = <0x06000ca0 0x20>;
966 reg = <0x06000800 0x400>;
1046 reg = <0x07000000 0x400>;
1047 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1057 reg = <0x07000400 0x400>;
1068 reg = <0x07000800 0x400>;
1079 reg = <0x07000c00 0x400>;
1090 reg = <0x07001000 0x400>;
1101 reg = <0x07001400 0x400>;
1112 reg = <0x07002800 0x400>;
1118 #size-cells = <0>;
1123 reg = <0x07002c00 0x400>;
1129 #size-cells = <0>;
1134 reg = <0x07003000 0x400>;
1140 #size-cells = <0>;
1145 reg = <0x07003400 0x400>;
1151 #size-cells = <0>;
1156 reg = <0x07003800 0x400>;
1162 #size-cells = <0>;
1167 reg = <0x08001000 0x20>;
1174 reg = <0x08001400 0x200>;
1178 reg = <0x080014b0 0x4>;
1187 reg = <0x080015a0 0xc>;
1195 pinctrl-0 = <&r_ir_pins>;
1199 reg = <0x08002000 0x40>;
1205 reg = <0x08002800 0x400>;
1216 reg = <0x08002c00 0x400>;
1219 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1241 reg = <0x08003400 0x400>;
1247 pinctrl-0 = <&r_rsb_pins>;
1250 #size-cells = <0>;