Lines Matching +full:0 +full:x01c20e00
111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
224 ranges = <0 0x00000000 0xc000>;
228 reg = <0x8000 0x4000>;
235 reg = <0x00010000 0x1000>;
238 ranges = <0 0x00010000 0x1000>;
240 otg_sram: sram-section@0 {
242 reg = <0x0000 0x1000>;
249 reg = <0x01d00000 0xd0000>;
252 ranges = <0 0x01d00000 0xd0000>;
254 ve_sram: sram-section@0 {
256 reg = <0x000000 0x80000>;
263 reg = <0x01c02000 0x1000>;
271 reg = <0x01c03000 0x1000>;
279 #size-cells = <0>;
284 reg = <0x01c05000 0x1000>;
293 #size-cells = <0>;
298 reg = <0x01c06000 0x1000>;
306 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
309 #size-cells = <0>;
314 reg = <0x01c0b000 0x1000>;
319 pinctrl-0 = <&emac_pins>;
325 reg = <0x01c0b080 0x14>;
328 #size-cells = <0>;
333 reg = <0x01c0c000 0x1000>;
344 #clock-cells = <0>;
349 #size-cells = <0>;
351 tcon0_in: port@0 {
353 #size-cells = <0>;
354 reg = <0>;
356 tcon0_in_be0: endpoint@0 {
357 reg = <0>;
369 #size-cells = <0>;
383 reg = <0x01c0d000 0x1000>;
394 #clock-cells = <0>;
399 #size-cells = <0>;
401 tcon1_in: port@0 {
403 #size-cells = <0>;
404 reg = <0>;
406 tcon1_in_be0: endpoint@0 {
407 reg = <0>;
419 #size-cells = <0>;
433 reg = <0x01c0e000 0x1000>;
444 reg = <0x01c0f000 0x1000>;
449 pinctrl-0 = <&mmc0_pins>;
452 #size-cells = <0>;
457 reg = <0x01c10000 0x1000>;
463 #size-cells = <0>;
468 reg = <0x01c11000 0x1000>;
474 #size-cells = <0>;
479 reg = <0x01c12000 0x1000>;
485 #size-cells = <0>;
490 reg = <0x01c13000 0x0400>;
494 phys = <&usbphy 0>;
496 extcon = <&usbphy 0>;
505 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
518 reg = <0x01c14000 0x100>;
528 reg = <0x01c14400 0x100>;
538 reg = <0x01c15000 0x1000>;
546 reg = <0x01c16000 0x1000>;
551 clock-names = "ahb", "mod", "pll-0", "pll-1";
560 #size-cells = <0>;
562 hdmi_in: port@0 {
564 #size-cells = <0>;
565 reg = <0>;
567 hdmi_in_tcon0: endpoint@0 {
568 reg = <0>;
586 reg = <0x01c17000 0x1000>;
595 #size-cells = <0>;
600 reg = <0x01c18000 0x1000>;
608 reg = <0x01c1c000 0x100>;
618 reg = <0x01c1c400 0x100>;
628 reg = <0x01c1d000 0x1000>;
638 reg = <0x01c1f000 0x1000>;
647 #size-cells = <0>;
652 reg = <0x01c20000 0x400>;
661 reg = <0x01c20400 0x400>;
668 reg = <0x01c20800 0x400>;
843 reg = <0x01c20c00 0x90>;
855 reg = <0x01c20c90 0x10>;
862 reg = <0x01c20d00 0x20>;
868 reg = <0x01c20e00 0xc>;
875 #sound-dai-cells = <0>;
877 reg = <0x01c21000 0x400>;
892 reg = <0x01c21800 0x40>;
901 reg = <0x01c21c00 0x40>;
906 #sound-dai-cells = <0>;
908 reg = <0x01c22400 0x400>;
920 reg = <0x01c22800 0x100>;
926 #sound-dai-cells = <0>;
928 reg = <0x01c22c00 0x40>;
940 reg = <0x01c23800 0x10>;
945 reg = <0x01c25000 0x100>;
947 #thermal-sensor-cells = <0>;
952 reg = <0x01c28000 0x400>;
962 reg = <0x01c28400 0x400>;
972 reg = <0x01c28800 0x400>;
982 reg = <0x01c28c00 0x400>;
992 reg = <0x01c29000 0x400>;
1002 reg = <0x01c29400 0x400>;
1012 reg = <0x01c29800 0x400>;
1022 reg = <0x01c29c00 0x400>;
1032 reg = <0x01c2a000 0x400>;
1040 reg = <0x01c2a400 0x400>;
1048 reg = <0x01c2ac00 0x400>;
1052 pinctrl-0 = <&i2c0_pins>;
1055 #size-cells = <0>;
1060 reg = <0x01c2b000 0x400>;
1064 pinctrl-0 = <&i2c1_pins>;
1067 #size-cells = <0>;
1072 reg = <0x01c2b400 0x400>;
1076 pinctrl-0 = <&i2c2_pins>;
1079 #size-cells = <0>;
1084 reg = <0x01c2bc00 0x400>;
1092 reg = <0x01c40000 0x10000>;
1113 reg = <0x01e00000 0x20000>;
1123 #size-cells = <0>;
1127 #size-cells = <0>;
1130 fe0_out_be0: endpoint@0 {
1131 reg = <0>;
1145 reg = <0x01e20000 0x20000>;
1155 #size-cells = <0>;
1159 #size-cells = <0>;
1162 fe1_out_be0: endpoint@0 {
1163 reg = <0>;
1177 reg = <0x01e40000 0x10000>;
1187 #size-cells = <0>;
1189 be1_in: port@0 {
1191 #size-cells = <0>;
1192 reg = <0>;
1194 be1_in_fe0: endpoint@0 {
1195 reg = <0>;
1207 #size-cells = <0>;
1210 be1_out_tcon0: endpoint@0 {
1211 reg = <0>;
1225 reg = <0x01e60000 0x10000>;
1235 #size-cells = <0>;
1237 be0_in: port@0 {
1239 #size-cells = <0>;
1240 reg = <0>;
1242 be0_in_fe0: endpoint@0 {
1243 reg = <0>;
1255 #size-cells = <0>;
1258 be0_out_tcon0: endpoint@0 {
1259 reg = <0>;