Lines Matching +full:0 +full:xb01b0080
28 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
40 reg = <0x1>;
47 reg = <0x2>;
55 reg = <0x3>;
73 #clock-cells = <0>;
79 #clock-cells = <0>;
90 reg = <0xb0020000 0x100>;
95 reg = <0xb0020200 0x100>;
102 reg = <0xb0020600 0x20>;
109 reg = <0xb0020620 0xe0>;
116 reg = <0xb0021000 0x1000>,
117 <0xb0020100 0x0100>;
124 reg = <0xb0022000 0x1000>;
134 reg = <0xb0120000 0x2000>;
142 reg = <0xb0122000 0x2000>;
150 reg = <0xb0124000 0x2000>;
158 reg = <0xb0126000 0x2000>;
166 reg = <0xb0128000 0x2000>;
174 reg = <0xb012a000 0x2000>;
182 reg = <0xb012c000 0x2000>;
190 reg = <0xb0160000 0x8000>;
198 reg = <0xb0170000 0x4000>;
202 #size-cells = <0>;
208 reg = <0xb0174000 0x4000>;
212 #size-cells = <0>;
218 reg = <0xb0178000 0x4000>;
222 #size-cells = <0>;
228 reg = <0xb017c000 0x4000>;
232 #size-cells = <0>;
238 reg = <0xb01b0200 0x4>;
248 reg = <0xb0168000 0x8000>;
258 reg = <0xb01b0100 0x100>;
264 reg = <0xb01b0000 0x40>, /* GPIO */
265 <0xb01b0040 0x10>, /* Multiplexing Control */
266 <0xb01b0060 0x18>, /* PAD Control */
267 <0xb01b0080 0xc>; /* PAD Drive Capacity */
270 gpio-ranges = <&pinctrl 0 0 132>;
283 reg = <0xb0260000 0xd00>;
297 reg = <0xb0230000 0x38>;
308 reg = <0xb0234000 0x38>;
319 reg = <0xb0238000 0x38>;
330 reg = <0xb0310000 0x10000>;
331 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;