Lines Matching +full:usb +full:- +full:dmac
1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <33333333>;
68 reg_5v0: regulator-5v0 {
69 compatible = "regulator-fixed";
71 regulator-name = "5v0-supply";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
76 cpu_intc: cpu-interrupt-controller {
77 compatible = "snps,archs-intc";
78 interrupt-controller;
79 #interrupt-cells = <1>;
82 idu_intc: idu-interrupt-controller {
83 compatible = "snps,archs-idu-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 interrupt-parent = <&cpu_intc>;
90 compatible = "snps,archs-pct";
91 interrupt-parent = <&cpu_intc>;
97 compatible = "snps,arc-timer";
99 interrupt-parent = <&cpu_intc>;
103 /* 64-bit Global Free Running Counter */
105 compatible = "snps,archs-timer-gfrc";
110 compatible = "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 interrupt-parent = <&idu_intc>;
117 cgu_rst: reset-controller@8a0 {
118 compatible = "snps,hsdk-reset";
119 #reset-cells = <1>;
123 core_clk: core-clk@0 {
124 compatible = "snps,hsdk-core-pll-clock";
126 #clock-cells = <0>;
134 assigned-clocks = <&core_clk>;
135 assigned-clock-rates = <1000000000>;
139 compatible = "snps,dw-apb-uart";
141 clock-frequency = <33330000>;
144 reg-shift = <2>;
145 reg-io-width = <4>;
149 compatible = "fixed-clock";
150 clock-frequency = <400000000>;
151 #clock-cells = <0>;
154 mmcclk_ciu: mmcclk-ciu {
155 compatible = "fixed-clock";
163 * divisor (div-by-2) in HSDK platform code.
167 clock-frequency = <50000000>;
168 #clock-cells = <0>;
171 mmcclk_biu: mmcclk-biu {
172 compatible = "fixed-clock";
173 clock-frequency = <400000000>;
174 #clock-cells = <0>;
177 gpu_core_clk: gpu-core-clk {
178 compatible = "fixed-clock";
179 clock-frequency = <400000000>;
180 #clock-cells = <0>;
183 gpu_dma_clk: gpu-dma-clk {
184 compatible = "fixed-clock";
185 clock-frequency = <400000000>;
186 #clock-cells = <0>;
189 gpu_cfg_clk: gpu-cfg-clk {
190 compatible = "fixed-clock";
191 clock-frequency = <200000000>;
192 #clock-cells = <0>;
195 dmac_core_clk: dmac-core-clk {
196 compatible = "fixed-clock";
197 clock-frequency = <400000000>;
198 #clock-cells = <0>;
201 dmac_cfg_clk: dmac-gpu-cfg-clk {
202 compatible = "fixed-clock";
203 clock-frequency = <200000000>;
204 #clock-cells = <0>;
208 #interrupt-cells = <1>;
212 interrupt-names = "macirq";
213 phy-mode = "rgmii-id";
215 snps,multicast-filter-bins = <256>;
217 clock-names = "stmmaceth";
218 phy-handle = <&phy0>;
220 reset-names = "stmmaceth";
221 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
222 dma-coherent;
224 tx-fifo-depth = <4096>;
225 rx-fifo-depth = <4096>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "snps,dwmac-mdio";
231 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
237 usb@60000 {
238 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
242 dma-coherent;
245 usb@40000 {
246 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
250 dma-coherent;
254 compatible = "altr,socfpga-dw-mshc";
256 num-slots = <1>;
257 fifo-depth = <16>;
258 card-detect-delay = <200>;
260 clock-names = "biu", "ciu";
262 bus-width = <4>;
263 dma-coherent;
267 compatible = "snps,dw-apb-ssi";
269 #address-cells = <1>;
270 #size-cells = <0>;
272 num-cs = <2>;
273 reg-io-width = <4>;
275 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
279 compatible = "sst26wf016b", "jedec,spi-nor";
281 #address-cells = <1>;
282 #size-cells = <1>;
283 spi-max-frequency = <4000000>;
289 vref-supply = <®_5v0>;
290 spi-max-frequency = <1000000>;
295 compatible = "snps,creg-gpio-hsdk";
297 gpio-controller;
298 #gpio-cells = <2>;
303 compatible = "snps,dw-apb-gpio";
305 #address-cells = <1>;
306 #size-cells = <0>;
308 gpio_port_a: gpio-controller@0 {
309 compatible = "snps,dw-apb-gpio-port";
310 gpio-controller;
311 #gpio-cells = <2>;
312 snps,nr-gpios = <24>;
324 clock-names = "bus", "reg", "core", "shader";
328 dmac: dmac@80000 { label
329 compatible = "snps,axi-dma-1.01a";
333 clock-names = "core-clk", "cfgr-clk";
335 dma-channels = <4>;
336 snps,dma-masters = <2>;
337 snps,data-width = <3>;
338 snps,block-size = <4096 4096 4096 4096>;
340 snps,axi-max-burst-len = <16>;
345 #address-cells = <2>;
346 #size-cells = <2>;