Lines Matching full:gate

350 /** @brief output of gate CLK_ENB_FUSE */
354  * @details output of gate CLK_ENB_GPU. This output connects to the GPU
360 /** @brief output of gate CLK_ENB_PCIE */
364 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
366 /** @brief output of gate CLK_ENB_PCIERX0*/
368 /** @brief output of gate CLK_ENB_PCIERX1*/
370 /** @brief output of gate CLK_ENB_PCIERX2*/
372 /** @brief output of gate CLK_ENB_PCIERX3*/
374 /** @brief output of gate CLK_ENB_PCIERX4*/
376 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
378 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
380 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
382 /** @brief output of gate CLK_ENB_SOR_SAFE */
390 /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
437 /** output of gate CLK_ENB_DTV */
441 /** @brief output of gate CLK_ENB_DP2 */
463 /** @brief output of gate CLK_ENB_CEC */
465 /** @brief output of gate CLK_ENB_DPAUX1 */
467 /** @brief output of gate CLK_ENB_DPAUX */
471 /** @brief output of gate CLK_ENB_HDA2HDMICODEC */
475 /** @brief output of gate CLK_ENB_SATA_OOB */
477 /** @brief output of gate CLK_ENB_SATA_IOBIST */
483 /** @brief output of gate CLK_ENB_APB2APE */
487 /** @brief output of gate CLK_ENB_IQC1 */
489 /** @brief output of gate CLK_ENB_IQC2 */
493 /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
495 /** @brief output of gate CLK_ENB_PLLC4_OUT */
505 /** @brief output of gate CLK_ENB_DSI */
507 /** @brief output of gate CLK_ENB_MIPI_CAL */
511 /** @brief output of gate CLK_ENB_DSIB */
539 /** @brief output of gate CLK_ENB_HSIC_TRK */
541 /** @brief output of gate CLK_ENB_USB2_TRK */
547 /** @brief output of gate CLK_ENB_ADSP */
549 /** @brief output of gate CLK_ENB_ADSPNEON */
553 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
557 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
559 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
561 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
585 /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
595 /** @brief output of gate CLK_ENB_EQOS */
597 /** @brief output of gate CLK_ENB_EQOS_RX */
647 /** @brief output of gate CLK_ENB_CAN1_HOST */
651 /** @brief output of gate CLK_ENB_CAN2_HOST */
685 /** @brief output of gate CLK_ENB_DSIC */
689 /** @brief output of gate CLK_ENB_DSID */
739 /** @brief output of gate CLK_ENB_PLLREFE_OUT */