Lines Matching full:five
111 #define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */
112 #define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */
113 #define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */
114 #define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */
115 #define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */
116 #define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */
117 #define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */
118 #define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */
119 #define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */
192 #define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */
193 #define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */
194 #define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */
195 #define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */
196 #define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */
197 #define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */
198 #define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */
199 #define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */
200 #define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
201 #define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */