Lines Matching +full:36 +full:- +full:41
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
50 #define CLK_MOUT_CMU_G2D_MSCL 36
55 #define CLK_MOUT_CMU_GDC_GDC0 41
279 #define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK 36
284 #define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 41
352 #define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 36
357 #define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 41
406 #define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36
411 #define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41
468 #define CLK_GOUT_MISC_QE_PDMA_ACLK 36
473 #define CLK_GOUT_MISC_QE_RTIC_PCLK 41
544 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36
549 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41
625 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36
630 #define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41