Lines Matching +full:usb +full:- +full:to +full:- +full:serial
5 of standard device types (network, serial, etc.) and miscellaneous
10 Each IP-core has a set of parameters which the FPGA designer can use to
12 extract the device parameters relevant to device drivers and copy them
15 to be recompiled every time the FPGA bitstream is resynthesized.
17 The new approach is to export the parameters into the device tree and
19 parameters which used to be exported as #defines will now become
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
33 (generic-name): an open firmware-style name that describes the
35 as 'serial' or 'ethernet'.
36 (ip-core-name): the name of the ip block (given after the BEGIN
38 and all underscores '_' converted to dashes '-'.
42 to lowercase and all underscore '_' characters are
43 converted to dashes '-'.
46 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
76 opb_uartlite_0: serial@ec100000 {
77 device_type = "serial";
78 compatible = "xlnx,opb-uartlite-1.00.b";
80 interrupt-parent = <&opb_intc_0>;
82 current-speed = <d#115200>; // standard serial device prop
83 clock-frequency = <d#50000000>; // standard serial device prop
84 xlnx,data-bits = <8>;
85 xlnx,odd-parity = <0>;
86 xlnx,use-parity = <0>;
89 That covers the general approach to binding xilinx IP cores into the
98 - resolution = <xres yres> : pixel resolution of framebuffer. Some
101 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
103 - rotate-display (empty) : rotate display 180 degrees.
107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
112 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
116 Xilinx Ethernet devices. In addition to general xilinx properties
117 listed above, nodes for these devices should include a phy-handle
119 like local-mac-address.
123 Xilinx uartlite devices are simple fixed speed serial ports.
126 - current-speed : Baud rate of uartlite
130 Xilinx hwicap devices provide access to the configuration logic
137 - xlnx,family : The family of the FPGA, necessary since the
141 - compatible : should contain "xlnx,xps-hwicap-1.00.a" or
142 "xlnx,opb-hwicap-1.00.b".
146 Xilinx UART 16550 devices are very similar to the NS16550 but with
150 - clock-frequency : Frequency of the clock input
151 - reg-offset : A value of 3 is required
152 - reg-shift : A value of 2 is required
154 vii) Xilinx USB Host controller
156 The Xilinx USB host controller is EHCI compatible but with a different
157 base address for the EHCI registers, and it is always a big-endian
158 USB Host controller. The hardware can be configured as high speed only,
162 - xlnx,support-usb-fs: A value 0 means the core is built as high speed